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Texas Instruments TMS320DM648 Video Capture Channel x Event Count Register VCxEVTCT, CAPEVTCT2

Models: TMS320DM648

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Video Capture Registers

3.13.9 Video Capture Channel x Event Count Register (VCxEVTCT)

The video capture channel x event count register (VCxEVTCT) is programmed with the number of EDMA events to be generated for each capture field.

An event counter tracks how many events have been generated and indicates which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter. Once the CAPEVTCTn number of events have been generated, the EDMA logic switches to the other threshold value. See Section 2.3.1.

The video capture channel x event count register (VCxEVTCT) is shown in Figure 3-29and described in Table 3-22.

Figure 3-29. Video Capture Channel x Event Count Register (VCxEVTCT)

31	28	27	16
	Reserved		CAPEVTCT2
	R-0		R/W-0
15	12	11	0
	Reserved		CAPEVTCT1
	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 3-22. Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions

					Description
Bit	field (1)	symval (1)	Value	BT.656 or Y/C Mode	Raw Data Mode	TCI Mode
31-28	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.
27-16	CAPEVTCT2	OF(value)	0-FFFh	Number of EDMA event sets	Not used.	Not used.
				(YEVT, CbEVT, CrEVT) to be
				generated for field 2 capture.
		DEFAULT	0
15-12	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.
11-0	CAPEVTCT1	OF(value)	0-FFFh	Number of EDMA event sets	Not used.	Not used.
				(YEVT, CbEVT, CrEVT) to be
				generated for field 1 capture.
		DEFAULT	0

(1)For CSL implementation, use the notation VP_VCxEVTCT_CAPEVTCTn_symval

3.13.10 Video Capture Channel B Control Register (VCBCTL)

Video capture is controlled by the video capture channel B control register (VCBCTL) shown in Figure 3-30and described in Table 3-23.

SPRUEM1 –May 2007

Video Capture Port

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Texas Instruments TMS320DM648 manual Video Capture Channel x Event Count Register VCxEVTCT, CAPEVTCT2, CAPEVTCT1

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values About This Manual Notational ConventionsRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port FifoBT.656 Video Capture Fifo Configuration Video Capture Fifo ConfigurationsYsrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo ConfigurationsBit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Capture Signal Mapping1 Video Display Signal MappingVideo Port Pin Mapping Capture Mode BT.656 Raw Data Data Bus Bit Vdin Bus Usage for Capture ModesVdin Data Bus Usage for Capture Modes1 Video Port Pin Multiplexing Vdout Data Bus Usage for Display ModesVideoPort Clocking Vdout Data Bus Usage for Display Modes1Video Port Power-On Reset Reset OperationPeripheral Bus Reset Software Port ResetCapture Channel Reset Display Channel ResetInterrupt Operation Capture Edma Event Generation Edma OperationEdma Size and Threshold Restrictions Display Edma Event GenerationVideo Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register NameVideo Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsDescription Operating Mode Video Port Operating Mode SelectionVideo Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Lfda DcnaLfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register VpisVideo Port Interrupt Status Register Vpis Field Descriptions Vdctl None ClearShort field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame OperationBT.656 Video Capture Mode Video Capture Mode SelectionVideo Capture Mode Selection 1 BT.656 Capture ChannelsBT.656 Protection Bits Error Correction by Protection BitsVideo Capture Parameters 3 BT.656 Image Window and Capture5 BT.656 Fifo Packing 4 BT.656 Data SamplingCommon Video Source Parameters Video Source1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture4 Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame OperationBit Y/C Fifo Packing VclkinaCapture Determination and Notification BT.656 and Y/C Mode Capture OperationVC xCTL Bit OperationVertical Synchronization Vertical Counter Reset PointVertical Synchronization Programming EAVVRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC =Horizontal Synchronization Horizontal Counter Reset PointHorizontal Synchronization Programming VCxCTL BitField Identification Field Identification ProgrammingField Detect Method Video Input Filtering Short and Long Field DetectVclkin VSYNC# VCTL2 HSYNC# VCTL1Input Filter Modes 10. Input Filter Mode SelectionChrominance Re-sampling Operation Scaling Operation2 Scaled Co-Sited Filtering Edge Pixel Replication11. Edge Pixel Replication Ancillary Data CaptureHorizontal Ancillary Hanc Data Capture Raw Data Capture ModeVertical Ancillary Vanc Data Capture Raw Data Capture Notification11. Raw Data Mode Capture Operation Raw Data Fifo PackingFrmc TCI Capture Mode TCI Capture FeaturesTCI Data Capture TCI Capture Error Detection Synchronizing the System ClockPCR TCI Data Capture Notification 12. TCI Capture Mode OperationVcactl Bit Clear FrmcWriting to the Fifo Reading from the FifoPerr Psterr Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C ModeCapturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C ModeCapturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeHandling Fifo Overrun Condition in TCI Capture Mode Video Capture Registers13. Video Capture Control Registers Video Capture Channel x Status Register VCASTAT, Vcbstat Fsync Frmc F2C F1C VcyposVcfld Vcxpos BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel a Control Register VcactlDescription Bit Rstch Blkcap None ResetRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde ResmplEavfid FDL Eavsav ExternV1EAV V0EAVVideo Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel x Field 1 Stop Register VCxSTOP1 Video Capture Channel x Field 2 Start Register VCxSTRT2 VcystopVcxstop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2Video Capture Channel B Control Register Vcbctl Video Capture Channel x Event Count Register VCxEVTCTCAPEVTCT2 CAPEVTCT1Vrst Hrst Vcen 30. Video Capture Channel B Control Register VcbctlSAV or VCTL1 inactive edge Not used BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI Capture Control Register Tcictl24. TCI Capture Control Register Tcictl Field Descriptions Inpcr TCI Clock Initialization LSB Register TciclkinitlBit Value Mode TCI Clock Initialization MSB Register TciclkinitmTCI System Time Clock LSB Register Tcistclkl TCI System Time Clock MSB Register Tcistclkm Default PcrmPcre Pcrm PcreTCI System Time Clock Compare LSB Register Tcistcmpl TCI System Time Clock Compare MSB Register TcistcmpmATC TCI System Time Clock Compare Mask LSB Register Tcistmskl Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask MSB Register Tcistmskm AtcmValue BT.656, Y/C Mode, or Raw Data Mode TCI M ode TCI System Time Clock Ticks Interrupt Register TciticksTickct Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw Data34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionDisplaying Video in BT.656 or Y/C Mode Video Display Field and Frame OperationVideo Display Registers Recommended Values Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing BT.656 Video Display Mode Sync Signal GenerationExternal Sync Operation Port Sync OperationFpcount Vclkout Display Timing Reference CodesLine Number BT.656 Frame TimingLine Number 525/60 Description3 BT.656 Image Display Blanking Codes4 BT.656 Fifo Unpacking Vclkout1 Y/C Display Timing Reference Codes Y/C Video Display Mode2 Y/C Blanking Codes 3 Y/C Image Display4 Y/C Fifo Unpacking Output Filter Mode SelectionVideo Output Filtering Output Filter Modes2x Co-Sited Scaling 15. Chrominance Re-sampling18. Output Edge Pixel Replication 2x Interspersed ScalingAncillary Data Display Raw Data Display ModeHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output SupportDisplay Determination and Notification Video Display Field and Frame OperationDisplay Operation Vdctl BitDisplay Line Boundary Conditions Video Display Event GenerationInterlaced BT.656 Timing Example Display Timing ExamplesIpcount =IMGSIZE78 YfifoVclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout FlcountFrmwidth = IMGHOFF1 = 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display ExampleVclkin Fpcount Ipcount VCTL1 HblnkabVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example VCTL1 Hblnkac VCTL1 Hsyncac Vclkout Frmwidth = IMGHOFF1 = Hblnkstart =Hsyncstart = 1350 Hsyncstop = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing ExampleDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Registers Video Display Status Register VdstatVideo Display Control Registers Video Display Status Register Vdstat Field Descriptions Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions Blanking Value BT.656 and Y/C Mode Raw Data ModeNone Frmdis None FlddisVideo Display Horizontal Blanking Register Vdhblnk Video Display Frame Size Register VdfrmszFrmheight FrmwidthField has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 ReservedVBLNKXSTOP1 VBLNKYSTOP1VBLNKXSTART2 VBLNKYSTART2DEFAULT0 Value BT.656 and Y/C ModeVBLNKYSTOP2 VBLNKXSTOP2IMGVOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGHOFF1 None NegoffVideo Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 Video Display Field 1 Timing Register VDFLDT1 Video Display Field 2 Image Size Register VDIMGSZ2IMGVSIZE2 IMGHSIZE2FLD1YSTART Video Display Field 2 Timing Register VDFLDT2FLD1XSTART FLD2YSTARTVDTHRLD2 Video Display Threshold Register VdthrldIncpix VDTHRLD1Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2Vrld Video Display Counter Reload Register VdreloadCrld Hrld CrldVideo Display Clipping Register Vdclip Video Display Event Register VddispevtDISPEVT2 DISPEVT1Clipchigh Video Display Default Display Value Register VddefvalCrdefval Cbdefval Video Display Vertical Interrupt Register VdvintDefval Crdefval56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register VdfbitFbitclr FbitsetVBITCLR1 VBITSET1VBITSET2 VBITCLR2Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value Video Display Fifo Registers Display Mode35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGeneral-Purpose I/O Operation Gpio Registers Video Port RegistersOffset Address Acronym Register Name Type Video Port Peripheral Identification Register VppidClass Revision ClassPeren Soft Free Video Port Peripheral Control Register PCRPeren StopVideo Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register PfuncNormal VDATA0TO9 Normal VDATA10TO19Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register PdirVDATA8TO9IN VDATA8TO9OUT VDATA12TO15IN VDATA12TO15OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUTVideo Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register PdinVideo Port Pin Data Out Register Pdout Field Descriptions Video Port Pin Data Output Register PdoutPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register PdsetVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register PdclrVideo Port Pin Interrupt Enable Register Pien PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2PIEN22 Value Description Video Port Pin Interrupt Polarity Register PipolPISTAT22 Video Port Pin Interrupt Status Register PistatNone VCTL3INT None VCTL2INTVideo Port Pin Interrupt Clear Register Piclr PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2PICLR22 Vcxo Interpolated Control Port VIC Port Signal Direction Description VIC Port Interface SignalsOverview InterfaceExample Values for Interpolation Rate Operational DetailsEnabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlVIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Products Applications DSPRfid