Texas Instruments TMS320DM648 manual VBLNKYSTOP1, VBLNKXSTOP1

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						Video Display Registers
	Figure 4-35. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
31		28	27			16
	Reserved				VBLNKYSTART1
	R-0				R/W-0
15		12	11			0
	Reserved				VBLNKXSTART1
	R-0				R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Table 4-10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Descriptions
					Description
Bit	field (1)	symval (1)		Value	BT.656 and Y/C Mode	Raw Data Mode
31-28	Reserved	-		0	Reserved. The reserved bit location is always read as 0. A value written to this
					field has no effect.

27-16 VBLNKYSTART1 OF(value)	0-FFFh Specifies the line (in FLCOUNT) where
	VBLNK active edge occurs for field 1.
	Does not affect EAV/SAV V bit
	operation.

Specifies the line (in FLCOUNT) where vertical blanking begins (VBLNK active edge) for field 1.

	DEFAULT	0
15-12 Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
			field has no effect.

11-0 VBLNKXSTART1 OF(value)	0-FFFh Specifies the pixel (in FPCOUNT)
	where VBLNK active edge occurs for
	field 1.
DEFAULT	0

(1)For CSL implementation, use the notation VP_VDVBLKS1_field_symval

Specifies the pixel (in FPCOUNT) where vertical blanking begins (VBLNK active edge) for field 1.

4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)

In raw data mode, VBLNK is de-asserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTOP1 (this is shown in Figure 4-6).

In BT.656 and Y/C mode, VBLNK is de-asserted whenever FLCOUNT = VBLNKYSTOP1 and FPCOUNT

=VBLNKXSTOP1. This VBLNK output control is completely independent of the timing control codes. The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.

The video display field 1 vertical blanking end register (VDVBLKE1) controls the end of vertical blanking in field 1.

The video display field 1 vertical blanking end register (VDVBLKE1) is shown in Figure 4-36and described in Table 4-11.

Figure 4-36. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)

31	28	27	16
	Reserved		VBLNKYSTOP1
	R-0		R/W-0
15	12	11	0
	Reserved		VBLNKXSTOP1
	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

SPRUEM1 –May 2007	Video Display Port	129
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