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Texas Instruments TMS320DM648 manual VDATA12TO15IN VDATA12TO15OUT, VDATA8TO9IN VDATA8TO9OUT

Models: TMS320DM648

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GPIO Registers

Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions (continued)

Bit	field (1)	symval (1)	Value	Description
12	PDIR12	OF(value)		PDIR12 bit controls the direction of the VDATA[15–12] pins.
		DEFAULT	0	Pins function as input.
		VDATA12TO15IN
		VDATA12TO15OUT	1	Pins function as output.
11-9	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.
8	PDIR8	OF(value)		PDIR8 bit controls the direction of the VDATA[9-8] pins.
		DEFAULT	0	Pins function as input.
		VDATA8TO9IN
		VDATA8TO9OUT		Pins function as output.
7-5	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.
4	PDIR4	OF(value)		PDIR4 bit controls the direction of the VDATA[7-4] pins.
		DEFAULT	0	Pins function as input.
		VDATA4TO7IN
		VDATA4TO7OUT	1	Pins function as output.
3-1	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.
0	PDIR0	OF(value)		PDIR0 bit controls the direction of the VDATA[3-2] pins.
		DEFAULT	0	Pins function as input.
		VDATA0T32IN
		VDATA0T32OUT	1	Pins function as output.

SPRUEM1 –May 2007	General-Purpose I/O Operation	157
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Texas Instruments TMS320DM648 manual VDATA12TO15IN VDATA12TO15OUT, VDATA8TO9IN VDATA8TO9OUT, VDATA4TO7IN VDATA4TO7OUT

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Notational Conventions About This ManualRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port FifoBT.656 Video Capture Fifo Configuration Video Capture Fifo ConfigurationsYsrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo ConfigurationsBit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Display Signal Mapping Video Capture Signal Mapping1Video Port Pin Mapping Vdin Bus Usage for Capture Modes Capture Mode BT.656 Raw Data Data Bus BitVdin Data Bus Usage for Capture Modes1 Video Port Pin Multiplexing Vdout Data Bus Usage for Display ModesVideoPort Clocking Vdout Data Bus Usage for Display Modes1Video Port Power-On Reset Reset OperationPeripheral Bus Reset Software Port ResetDisplay Channel Reset Capture Channel ResetInterrupt Operation Capture Edma Event Generation Edma OperationEdma Size and Threshold Restrictions Display Edma Event GenerationVideo Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register NameVideo Port Control Register Vpctl Field Descriptions Video Port Control Register VpctlDescription Operating Mode Video Port Operating Mode SelectionVideo Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Lfda DcnaLfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register VpisVideo Port Interrupt Status Register Vpis Field Descriptions Vdctl None ClearShort field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame OperationBT.656 Video Capture Mode Video Capture Mode SelectionVideo Capture Mode Selection 1 BT.656 Capture ChannelsBT.656 Protection Bits Error Correction by Protection BitsVideo Capture Parameters 3 BT.656 Image Window and Capture5 BT.656 Fifo Packing 4 BT.656 Data SamplingCommon Video Source Parameters Video Source1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture4 Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame OperationBit Y/C Fifo Packing VclkinaCapture Determination and Notification BT.656 and Y/C Mode Capture OperationVC xCTL Bit OperationVertical Synchronization Vertical Counter Reset PointVertical Synchronization Programming EAVVRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC =Horizontal Synchronization Horizontal Counter Reset PointHorizontal Synchronization Programming VCxCTL BitField Identification Programming Field IdentificationField Detect Method Video Input Filtering Short and Long Field DetectVclkin VSYNC# VCTL2 HSYNC# VCTL1Input Filter Modes 10. Input Filter Mode SelectionChrominance Re-sampling Operation Scaling Operation2 Scaled Co-Sited Filtering Edge Pixel Replication11. Edge Pixel Replication Ancillary Data CaptureHorizontal Ancillary Hanc Data Capture Raw Data Capture ModeVertical Ancillary Vanc Data Capture Raw Data Capture NotificationRaw Data Fifo Packing 11. Raw Data Mode Capture OperationFrmc TCI Capture Features TCI Capture ModeTCI Data Capture Synchronizing the System Clock TCI Capture Error DetectionPCR TCI Data Capture Notification 12. TCI Capture Mode OperationVcactl Bit Clear FrmcReading from the Fifo Writing to the FifoPerr Psterr Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C ModeCapturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C ModeCapturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeVideo Capture Registers Handling Fifo Overrun Condition in TCI Capture Mode13. Video Capture Control Registers Fsync Frmc F2C F1C Vcypos Video Capture Channel x Status Register VCASTAT, VcbstatVcfld Vcxpos Video Capture Channel a Control Register Vcactl BT.656 or Y/C Mode Raw Data Mode TCI ModeDescription Bit Rstch Blkcap None ResetRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde ResmplEavfid FDL Eavsav ExternV1EAV V0EAVVideo Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel x Field 1 Stop Register VCxSTOP1 Vcystop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcxstop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2Video Capture Channel B Control Register Vcbctl Video Capture Channel x Event Count Register VCxEVTCTCAPEVTCT2 CAPEVTCT1Vrst Hrst Vcen 30. Video Capture Channel B Control Register VcbctlSAV or VCTL1 inactive edge Not used TCI Capture Control Register Tcictl BT.656, Y/C Mode, or Raw Data Mode TCI Mode24. TCI Capture Control Register Tcictl Field Descriptions Inpcr TCI Clock Initialization LSB Register TciclkinitlTCI Clock Initialization MSB Register Tciclkinitm Bit Value ModeTCI System Time Clock LSB Register Tcistclkl TCI System Time Clock MSB Register Tcistclkm Default PcrmPcre Pcrm PcreTCI System Time Clock Compare MSB Register Tcistcmpm TCI System Time Clock Compare LSB Register TcistcmplATC TCI System Time Clock Compare Mask LSB Register Tcistmskl Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask MSB Register Tcistmskm AtcmTCI System Time Clock Ticks Interrupt Register Tciticks Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTickct Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw Data34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Field and Frame Operation Displaying Video in BT.656 or Y/C ModeVideo Display Registers Recommended Values Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing BT.656 Video Display Mode Sync Signal GenerationExternal Sync Operation Port Sync OperationFpcount Vclkout Display Timing Reference CodesLine Number BT.656 Frame TimingLine Number 525/60 Description3 BT.656 Image Display Blanking Codes4 BT.656 Fifo Unpacking Vclkout1 Y/C Display Timing Reference Codes Y/C Video Display Mode2 Y/C Blanking Codes 3 Y/C Image Display4 Y/C Fifo Unpacking Output Filter Mode SelectionVideo Output Filtering Output Filter Modes2x Co-Sited Scaling 15. Chrominance Re-sampling18. Output Edge Pixel Replication 2x Interspersed ScalingAncillary Data Display Raw Data Display ModeHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output SupportDisplay Determination and Notification Video Display Field and Frame OperationDisplay Operation Vdctl BitDisplay Line Boundary Conditions Video Display Event GenerationInterlaced BT.656 Timing Example Display Timing ExamplesIpcount =IMGSIZE78 YfifoFlcount Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display ExampleIpcount VCTL1 Hblnkab Vclkin FpcountVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Frmwidth = IMGHOFF1 = Hblnkstart = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutHsyncstart = 1350 Hsyncstop = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing ExampleDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Status Register Vdstat Video Display RegistersVideo Display Control Registers Video Display Status Register Vdstat Field Descriptions Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions Blanking Value BT.656 and Y/C Mode Raw Data ModeNone Frmdis None FlddisVideo Display Horizontal Blanking Register Vdhblnk Video Display Frame Size Register VdfrmszFrmheight FrmwidthField has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 ReservedVBLNKXSTOP1 VBLNKYSTOP1VBLNKXSTART2 VBLNKYSTART2DEFAULT0 Value BT.656 and Y/C ModeVBLNKYSTOP2 VBLNKXSTOP2IMGVOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGHOFF1 None NegoffIMGVSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGHSIZE1 IMGVOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGHOFF2 Video Display Field 1 Timing Register VDFLDT1 Video Display Field 2 Image Size Register VDIMGSZ2IMGVSIZE2 IMGHSIZE2FLD1YSTART Video Display Field 2 Timing Register VDFLDT2FLD1XSTART FLD2YSTARTVDTHRLD2 Video Display Threshold Register VdthrldIncpix VDTHRLD1Hsyncstop Video Display Horizontal Synchronization Register VdhsyncHsyncstart VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2Vrld Video Display Counter Reload Register VdreloadCrld Hrld CrldVideo Display Clipping Register Vdclip Video Display Event Register VddispevtDISPEVT2 DISPEVT1Clipchigh Video Display Default Display Value Register VddefvalCrdefval Cbdefval Video Display Vertical Interrupt Register VdvintDefval Crdefval56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register VdfbitFbitclr FbitsetVBITCLR1 VBITSET1VBITSET2 VBITCLR234. Video Display Register Recommended Values Video Display Registers Recommended ValuesRegister Field 525/60 Value Video Display Fifo Registers Display Mode35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGeneral-Purpose I/O Operation Video Port Registers Gpio RegistersOffset Address Acronym Register Name Type Video Port Peripheral Identification Register VppidClass Revision ClassPeren Soft Free Video Port Peripheral Control Register PCRPeren StopVideo Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register PfuncNormal VDATA0TO9 Normal VDATA10TO19Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register PdirVDATA8TO9IN VDATA8TO9OUT VDATA12TO15IN VDATA12TO15OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUTVideo Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register PdinVideo Port Pin Data Out Register Pdout Field Descriptions Video Port Pin Data Output Register PdoutPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register PdsetVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register PdclrPIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Video Port Pin Interrupt Enable Register PienPIEN22 Value Description Video Port Pin Interrupt Polarity Register PipolPISTAT22 Video Port Pin Interrupt Status Register PistatNone VCTL3INT None VCTL2INTPICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Video Port Pin Interrupt Clear Register PiclrPICLR22 Vcxo Interpolated Control Port VIC Port Signal Direction Description VIC Port Interface SignalsOverview InterfaceExample Values for Interpolation Rate Operational DetailsVIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlVIC Input Register Vicin Field Descriptions VIC Input Register VicinVicinbits VIC Clock Divider Register Vicdiv Field Descriptions VIC Clock Divider Register VicdivVicclkdiv DSP Products ApplicationsRfid