Texas Instruments TMS320DM648 manual 30. Y/C Progressive Display Vertical Timing Example

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Display Timing Examples

The vertical output timing is shown in Figure 4-30. SMPTE 296M has a single active field 1 that is

720-lines high. This example shows the 716-line image window with an IMGVOFFn of 3 lines and also results in a non-data line at the end of the field.

The VBLNK and VSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally. The VBLNK and VSYNC edges occur at the end of an active line so their XSTART/XSTOP values are set to 1280 (start of blanking). The field 2 vertical timing start and stop registers are programmed to a value greater than 750. Since this value is never reached by FLCOUNT, no extra VBLNK or VSYNC transitions occur. For true SMPTE 296M operation, neither VBLNK nor VSYNC would be used.

The FLD output is setup to transition low at the start of each frame. Since the FLD2YSTART value is never reached by FLCOUNT, the FLD output remains always low.

The ILCOUNT operation follows the description in Section 4.1.2. ILCOUNT resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFn) and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The operation during non-display time is not a requirement, it could continue counting until the next FLCOUNT = VBLNKSTOPx + IMGVOFFn point or it could reset immediately after IMGVSIZEx or when FLCOUNT is reset.

The active horizontal output column shows the output data during the active portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set to enable the default output.

Figure 4-30. Y/C Progressive Display Vertical Timing Example

FLCOUNT

EAV ILCOUNT V F

	(A)(B)
FLD	VBLNK

VSYNC(A)(B)

Active

Horizontal

Output

750

1

2

3

4

5

6

25

26

27

28

29

744

745

746

747

748

749

750

1

Field 1 Blanking

Field 1 Active

Field 1 Image

Field 1 Blanking

716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	0	0
716	0	0
716	0	0

10 0

20 0

7150 0

7160 0

716	0	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0
716	1	0

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Default Value(B)

Default Value(B)

Default Value(B)

FIFO Data

FIFO Data

FIFO Data

FIFO Data

Default Value(B)

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

Blanking Value

AAssumes VCT1P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK output when VCTL2S bit is set 01.

BIf DVEN bit in VDCTL is set to 1; otherwise, blanking value is output

118	Video Display Port	SPRUEM1 –May 2007
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