Texas Instruments TMS320DM648 manual Bit BT.656 Fifo Unpacking

3-39	TCI System Time Clock Compare Mask MSB Register (TCISTMSKM)		90
3-40	TCI System Time Clock Ticks Interrupt Register (TCITICKS)		90
4-1	NTSC Compatible Interlaced Display		93
4-2	SMPTE 296M Compatible Progressive Scan Display		94
4-3	Interlaced Blanking Intervals and Video Areas		95
4-4	Progressive Blanking Intervals and Video Area		96
4-5	Horizontal Blanking and Horizontal Sync Timing		97
4-6	Vertical Blanking, Sync and Even/Odd Frame Signal Timing		97
4-7	Video Display Module Synchronization Chain		98
4-8	BT.656 Output Sequence		98
4-9	525/60 BT.656 Horizontal Blanking Timing		99
4-10	625/50 BT.656 Horizontal Blanking Timing		99
4-11	Digital Vertical F and V Transitions		100
4-12	8-Bit BT.656 FIFO Unpacking		101
4-13	Y/C Horizontal Blanking Timing (BT.1120 60I)		102
4-14	8-Bit Y/C FIFO Unpacking		103
4-15	Chrominance Re-sampling		104
4-16	2x Co-Sited Scaling		104
4-17	2x Interspersed Scaling		105
4-18	Output Edge Pixel Replication		105
4-19	Luma Edge Replication		105
4-20	Interspersed Chroma Edge Replication		106
4-21	8-Bit Raw FIFO Unpacking		107
4-22	16-Bit Raw FIFO Unpacking		107
4-23	8-Bit Raw FIFO Unpacking		107
4-24	Display Line Boundary Example		110
4-25	BT.656 Interlaced Display Horizontal Timing Example		111
4-26	BT.656 Interlaced Display Vertical Timing Example		113
4-27	Raw Interlaced Display Horizontal Timing Example		114
4-28	Raw Interlaced Display Vertical Timing Example		115
4-29	Y/C Progressive Display Horizontal Timing Example		117
4-30	Y/C Progressive Display Vertical Timing Example		118
4-31	Video Display Status Register (VDSTAT)		123
4-32	Video Display Control Register (VDCTL)		124
4-33	Video Display Frame Size Register (VDFRMSZ)		127
4-34	Video Display Horizontal Blanking Register (VDHBLNK)		128
4-35	Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)		129
4-36	Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)		129
4-37	Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)		130
4-38	Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)		131
4-39	Video Display Field 1 Image Offset Register (VDIMGOFF1)		132
4-40	Video Display Field 1 Image Size Register (VDIMGSZ1)		133
4-41	Video Display Field 2 Image Offset Register (VDIMGOFF2)		134
4-42	Video Display Field 2 Image Size Register (VDIMGSZ2)		135
4-43	Video Display Field 1 Timing Register (VDFLDT1)		136
4-44	Video Display Field 2 Timing Register (VDFLDT2)		136
4-45	Video Display Threshold Register (VDTHRLD)		137
4-46	Video Display Horizontal Synchronization Register (VDHSYNC)		138
4-47	Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)		139
4-48	Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)		139
4-49	Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)		140
4-50	Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)		141
4-51	Video Display Counter Reload Register (VDRELOAD)		141
SPRUEM1 –May 2007		List of Figures	9

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