Flcount, Frmwidth = IMGHOFF1 = | Texas Instruments TMS320DM648

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Display Timing Examples

VCLKIN

FPCOUNT

IPCOUNT

VCTL1 (HBLNK)(A)(C)

VCTL1 (HSYNC)(A)(C)

VCLKOUT

VDOUT[9−2]

FLCOUNT

Figure 4-25. BT.656 Interlaced Display Horizontal Timing Example

4			268			4							1440
					One Line													Next
																		Line
720 721	722	723	735 736	799	800	855 856	857 0	1	7	8		9	10	710 711 712		718 719		720 721
703 703 703		703	703 703	703	703	703 703 703 703 703			703		0	1	2	702 703	703	703	703 703 703
								(B)
													Display
			Blanking										Image
			Blanking										Active Video
Def Cr Def Y FF.C 00.0	00.0 XY.0	80.0 10.0 80.0	10.0			80.0 10.0 80.0 10.0	FF.C 00.0 00.0 XY.0	Def Cb Def Y Def Cr Def Y		Def Cr	Def Y	Cb0 Y0	Cr0 Y1 Cb1 Y2	Cb351 Y702	Cr351 Y703 Def Cb Def Y	Def Cb Def Y		Def Cr Def Y FF.C 00.0 00.0 XY.0
EAV Blanking Data							SAV											EAV
n − 1						n												n + 1

FRMWIDTH = 858	IMGHOFF1 = 8	HSYNCSTART = 736
HBLNKSTART = 720	IMGHSIZE1 = 704	HSYNCSTOP = 800
HBLNKSTOP = 856	IMGHOFF2 = 8
	IMGHSIZE2 = 704

AAssumes VCT0P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.

BHBLNK operation when HBDLA bit in VDHBLNK is set to 1.

CDiagram assumes a two VCLK pipeline delay between internal counters and output signals.

SPRUEM1 –May 2007	Video Display Port	111
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Texas Instruments TMS320DM648 Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout, Flcount, Frmwidth = IMGHOFF1 =

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values About This Manual Notational ConventionsRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port Fifo BT.656 Video Capture Fifo Configuration Video Capture Fifo Configurations Ysrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo Configurations Bit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo Configuration Video Capture Signal Mapping1 Video Display Signal MappingVideo Port Pin Mapping Capture Mode BT.656 Raw Data Data Bus Bit Vdin Bus Usage for Capture ModesVdin Data Bus Usage for Capture Modes1 Vdout Data Bus Usage for Display Modes1 Vdout Data Bus Usage for Display ModesVideo Port Pin Multiplexing VideoPort Clocking Video Port Software Port Reset Reset OperationPower-On Reset Peripheral Bus Reset Capture Channel Reset Display Channel ResetInterrupt Operation Capture Edma Event Generation Edma Operation Edma Size and Threshold Restrictions Display Edma Event Generation Acronym Register Name Edma Interface OperationVideo Port Control Registers Video Port Control Registers Video Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsDescription Operating Mode Video Port Operating Mode Selection Video Port Status Register Vpstat Field Descriptions Video Port Status Register Vpstat Video Port Interrupt Enable Register Vpie Lfda Dcna Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register Vpis Video Port Interrupt Status Register Vpis Field Descriptions Vdctl None Clear Short field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame Operation 1 BT.656 Capture Channels Video Capture Mode SelectionBT.656 Video Capture Mode Video Capture Mode Selection BT.656 Protection Bits Error Correction by Protection Bits Video Capture Parameters 3 BT.656 Image Window and Capture Video Source 4 BT.656 Data Sampling5 BT.656 Fifo Packing Common Video Source Parameters 3 Y/C Image Window and Capture Y/C Video Capture Mode1 Y/C Capture Channels 2 Y/C Timing Reference Codes Vclkina BT.656 and Y/C Mode Field and Frame Operation4 Y/C Fifo Packing Bit Y/C Fifo Packing Operation BT.656 and Y/C Mode Capture OperationCapture Determination and Notification VC xCTL Bit EAV Vertical Counter Reset PointVertical Synchronization Vertical Synchronization Programming VRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC = VCxCTL Bit Horizontal Counter Reset PointHorizontal Synchronization Horizontal Synchronization Programming Field Identification Field Identification ProgrammingField Detect Method HSYNC# VCTL1 Short and Long Field DetectVideo Input Filtering Vclkin VSYNC# VCTL2 Scaling Operation 10. Input Filter Mode SelectionInput Filter Modes Chrominance Re-sampling Operation 2 Scaled Co-Sited Filtering Edge Pixel Replication 11. Edge Pixel Replication Ancillary Data Capture Raw Data Capture Notification Raw Data Capture ModeHorizontal Ancillary Hanc Data Capture Vertical Ancillary Vanc Data Capture 11. Raw Data Mode Capture Operation Raw Data Fifo PackingFrmc TCI Capture Mode TCI Capture FeaturesTCI Data Capture TCI Capture Error Detection Synchronizing the System ClockPCR Clear Frmc 12. TCI Capture Mode OperationTCI Data Capture Notification Vcactl Bit Writing to the Fifo Reading from the FifoPerr Psterr Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data Mode Handling Fifo Overrun Condition in TCI Capture Mode Video Capture Registers13. Video Capture Control Registers Video Capture Channel x Status Register VCASTAT, Vcbstat Fsync Frmc F2C F1C VcyposVcfld Vcxpos BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel a Control Register VcactlDescription Bit Lfde Sfde Resmpl None ResetRstch Blkcap Rdfe Finv EXC Fldd Vrst Hrst Vcen V0EAV Eavsav ExternEavfid FDL V1EAV Video Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Stop Register VCxSTOP1 Video Capture Channel x Field 2 Start Register VCxSTRT2 VcystopVcxstop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2 CAPEVTCT1 Video Capture Channel x Event Count Register VCxEVTCTVideo Capture Channel B Control Register Vcbctl CAPEVTCT2 Vrst Hrst Vcen 30. Video Capture Channel B Control Register Vcbctl SAV or VCTL1 inactive edge Not used BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI Capture Control Register Tcictl24. TCI Capture Control Register Tcictl Field Descriptions Inpcr TCI Clock Initialization LSB Register Tciclkinitl Bit Value Mode TCI Clock Initialization MSB Register TciclkinitmTCI System Time Clock LSB Register Tcistclkl Pcre Default PcrmTCI System Time Clock MSB Register Tcistclkm Pcre Pcrm TCI System Time Clock Compare LSB Register Tcistcmpl TCI System Time Clock Compare MSB Register TcistcmpmATC Atcm Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask LSB Register Tcistmskl TCI System Time Clock Compare Mask MSB Register Tcistmskm Value BT.656, Y/C Mode, or Raw Data Mode TCI M ode TCI System Time Clock Ticks Interrupt Register TciticksTickct 35. Video Capture Fifo Registers Function Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 34. Video Capture Fifo Registers Displaying Video in BT.656 or Y/C Mode Video Display Field and Frame OperationVideo Display Registers Recommended Values Image Timing Video Display Mode SelectionVideo Display Mode Selection Dmode Bits Mode Description Smpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display Counters Horizontal Blanking and Horizontal Sync Timing Port Sync Operation Sync Signal GenerationBT.656 Video Display Mode External Sync Operation Fpcount Vclkout Display Timing Reference Codes 525/60 Description BT.656 Frame TimingLine Number Line Number Vclkout Blanking Codes3 BT.656 Image Display 4 BT.656 Fifo Unpacking 3 Y/C Image Display Y/C Video Display Mode1 Y/C Display Timing Reference Codes 2 Y/C Blanking Codes Output Filter Modes Output Filter Mode Selection4 Y/C Fifo Unpacking Video Output Filtering 2x Co-Sited Scaling 15. Chrominance Re-sampling 18. Output Edge Pixel Replication 2x Interspersed Scaling Vertical Ancillary Vanc Data Display Raw Data Display ModeAncillary Data Display Horizontal Ancillary Hanc Data Display Raw Data Fifo Unpacking Raw Mode RGB Output Support Vdctl Bit Video Display Field and Frame OperationDisplay Determination and Notification Display Operation Display Line Boundary Conditions Video Display Event Generation Yfifo Display Timing ExamplesInterlaced BT.656 Timing Example Ipcount =IMGSIZE78 Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout FlcountFrmwidth = IMGHOFF1 = 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example Vclkin Fpcount Ipcount VCTL1 HblnkabVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example VCTL1 Hblnkac VCTL1 Hsyncac Vclkout Frmwidth = IMGHOFF1 = Hblnkstart =Hsyncstart = 1350 Hsyncstop = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Registers Video Display Status Register VdstatVideo Display Control Registers Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl Video Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field Descriptions None Flddis Value BT.656 and Y/C Mode Raw Data ModeBlanking None Frmdis Frmwidth Video Display Frame Size Register VdfrmszVideo Display Horizontal Blanking Register Vdhblnk Frmheight Field has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved VBLNKXSTOP1 VBLNKYSTOP1 VBLNKXSTART2 VBLNKYSTART2 VBLNKXSTOP2 Value BT.656 and Y/C ModeDEFAULT0 VBLNKYSTOP2 None Negoff Video Display Field 1 Image Offset Register VDIMGOFF1IMGVOFF1 IMGHOFF1 Video Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 IMGHSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2Video Display Field 1 Timing Register VDFLDT1 IMGVSIZE2 FLD2YSTART Video Display Field 2 Timing Register VDFLDT2FLD1YSTART FLD1XSTART VDTHRLD1 Video Display Threshold Register VdthrldVDTHRLD2 Incpix Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCXSTOP1 VSYNCXSTART1VSYNCYSTART1 VSYNCYSTOP1 VSYNCYSTART2 VSYNCXSTART2 Crld Video Display Counter Reload Register VdreloadVrld Crld Hrld DISPEVT1 Video Display Event Register VddispevtVideo Display Clipping Register Vdclip DISPEVT2 Clipchigh Video Display Default Display Value Register Vddefval Crdefval Video Display Vertical Interrupt Register VdvintCrdefval Cbdefval Defval 56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register Vdfbit VBITSET1 FbitsetFbitclr VBITCLR1 VBITSET2 VBITCLR2 Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value 36. Video Display Fifo Registers Function Display ModeVideo Display Fifo Registers 35. Video Display Fifo Registers General-Purpose I/O Operation Gpio Registers Video Port RegistersOffset Address Acronym Register Name Class Video Port Peripheral Identification Register VppidType Class Revision Stop Video Port Peripheral Control Register PCRPeren Soft Free Peren Video Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register Pfunc Normal VDATA0TO9 Normal VDATA10TO19 Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register Pdir VDATA0T32IN VDATA0T32OUT VDATA12TO15IN VDATA12TO15OUTVDATA8TO9IN VDATA8TO9OUT VDATA4TO7IN VDATA4TO7OUT Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register Pdin PDOUT22 Video Port Pin Data Output Register PdoutVideo Port Pin Data Out Register Pdout Field Descriptions PDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register Pdset Video Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register Pdclr Video Port Pin Interrupt Enable Register Pien PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2PIEN22 Value Description Video Port Pin Interrupt Polarity Register Pipol None VCTL2INT Video Port Pin Interrupt Status Register PistatPISTAT22 None VCTL3INT Video Port Pin Interrupt Clear Register Piclr PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2PICLR22 Vcxo Interpolated Control Port Interface VIC Port Interface SignalsVIC Port Signal Direction Description Overview Example Values for Interpolation Rate Operational Details Enabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register Vicctl VIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Products Applications DSPRfid