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Texas Instruments TMS320DM648 Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout, Flcount

Models: TMS320DM648

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Display Timing Examples

VCLKIN

FPCOUNT

IPCOUNT

VCTL1 (HBLNK)(A)(C)

VCTL1 (HSYNC)(A)(C)

VCLKOUT

VDOUT[9−2]

FLCOUNT

Figure 4-25. BT.656 Interlaced Display Horizontal Timing Example

4			268			4							1440
					One Line													Next
																		Line
720 721	722	723	735 736	799	800	855 856	857 0	1	7	8		9	10	710 711 712		718 719		720 721
703 703 703		703	703 703	703	703	703 703 703 703 703			703		0	1	2	702 703	703	703	703 703 703
								(B)
													Display
			Blanking										Image
			Blanking										Active Video
Def Cr Def Y FF.C 00.0	00.0 XY.0	80.0 10.0 80.0	10.0			80.0 10.0 80.0 10.0	FF.C 00.0 00.0 XY.0	Def Cb Def Y Def Cr Def Y		Def Cr	Def Y	Cb0 Y0	Cr0 Y1 Cb1 Y2	Cb351 Y702	Cr351 Y703 Def Cb Def Y	Def Cb Def Y		Def Cr Def Y FF.C 00.0 00.0 XY.0
EAV Blanking Data							SAV											EAV
n − 1						n												n + 1

FRMWIDTH = 858	IMGHOFF1 = 8	HSYNCSTART = 736
HBLNKSTART = 720	IMGHSIZE1 = 704	HSYNCSTOP = 800
HBLNKSTOP = 856	IMGHOFF2 = 8
	IMGHSIZE2 = 704

AAssumes VCT0P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.

BHBLNK operation when HBDLA bit in VDHBLNK is set to 1.

CDiagram assumes a two VCLK pipeline delay between internal counters and output signals.

SPRUEM1 –May 2007	Video Display Port	111
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Texas Instruments TMS320DM648 Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout, Flcount, Frmwidth = IMGHOFF1 =

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values About This Manual Notational ConventionsRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port FifoBT.656 Video Capture Fifo Configuration Video Capture Fifo ConfigurationsYsrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo ConfigurationsBit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Capture Signal Mapping1 Video Display Signal MappingVideo Port Pin Mapping Capture Mode BT.656 Raw Data Data Bus Bit Vdin Bus Usage for Capture ModesVdin Data Bus Usage for Capture Modes1 Vdout Data Bus Usage for Display Modes1 Vdout Data Bus Usage for Display ModesVideo Port Pin Multiplexing VideoPort ClockingVideo Port Software Port Reset Reset OperationPower-On Reset Peripheral Bus ResetCapture Channel Reset Display Channel ResetInterrupt Operation Capture Edma Event Generation Edma OperationEdma Size and Threshold Restrictions Display Edma Event GenerationAcronym Register Name Edma Interface OperationVideo Port Control Registers Video Port Control RegistersVideo Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsDescription Operating Mode Video Port Operating Mode SelectionVideo Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Lfda DcnaLfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register VpisVideo Port Interrupt Status Register Vpis Field Descriptions Vdctl None ClearShort field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame Operation1 BT.656 Capture Channels Video Capture Mode SelectionBT.656 Video Capture Mode Video Capture Mode SelectionBT.656 Protection Bits Error Correction by Protection BitsVideo Capture Parameters 3 BT.656 Image Window and CaptureVideo Source 4 BT.656 Data Sampling5 BT.656 Fifo Packing Common Video Source Parameters3 Y/C Image Window and Capture Y/C Video Capture Mode1 Y/C Capture Channels 2 Y/C Timing Reference CodesVclkina BT.656 and Y/C Mode Field and Frame Operation4 Y/C Fifo Packing Bit Y/C Fifo PackingOperation BT.656 and Y/C Mode Capture OperationCapture Determination and Notification VC xCTL BitEAV Vertical Counter Reset PointVertical Synchronization Vertical Synchronization ProgrammingVRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC =VCxCTL Bit Horizontal Counter Reset PointHorizontal Synchronization Horizontal Synchronization ProgrammingField Identification Field Identification ProgrammingField Detect Method HSYNC# VCTL1 Short and Long Field DetectVideo Input Filtering Vclkin VSYNC# VCTL2Scaling Operation 10. Input Filter Mode SelectionInput Filter Modes Chrominance Re-sampling Operation2 Scaled Co-Sited Filtering Edge Pixel Replication11. Edge Pixel Replication Ancillary Data CaptureRaw Data Capture Notification Raw Data Capture ModeHorizontal Ancillary Hanc Data Capture Vertical Ancillary Vanc Data Capture11. Raw Data Mode Capture Operation Raw Data Fifo PackingFrmc TCI Capture Mode TCI Capture FeaturesTCI Data Capture TCI Capture Error Detection Synchronizing the System ClockPCR Clear Frmc 12. TCI Capture Mode OperationTCI Data Capture Notification Vcactl BitWriting to the Fifo Reading from the FifoPerr Psterr Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C ModeCapturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C ModeCapturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeHandling Fifo Overrun Condition in TCI Capture Mode Video Capture Registers13. Video Capture Control Registers Video Capture Channel x Status Register VCASTAT, Vcbstat Fsync Frmc F2C F1C VcyposVcfld Vcxpos BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel a Control Register VcactlDescription Bit Lfde Sfde Resmpl None ResetRstch Blkcap Rdfe Finv EXC Fldd Vrst Hrst VcenV0EAV Eavsav ExternEavfid FDL V1EAVVideo Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel x Field 1 Stop Register VCxSTOP1 Video Capture Channel x Field 2 Start Register VCxSTRT2 VcystopVcxstop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2CAPEVTCT1 Video Capture Channel x Event Count Register VCxEVTCTVideo Capture Channel B Control Register Vcbctl CAPEVTCT2Vrst Hrst Vcen 30. Video Capture Channel B Control Register VcbctlSAV or VCTL1 inactive edge Not used BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI Capture Control Register Tcictl24. TCI Capture Control Register Tcictl Field Descriptions Inpcr TCI Clock Initialization LSB Register TciclkinitlBit Value Mode TCI Clock Initialization MSB Register TciclkinitmTCI System Time Clock LSB Register Tcistclkl Pcre Default PcrmTCI System Time Clock MSB Register Tcistclkm Pcre PcrmTCI System Time Clock Compare LSB Register Tcistcmpl TCI System Time Clock Compare MSB Register TcistcmpmATC Atcm Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask LSB Register Tcistmskl TCI System Time Clock Compare Mask MSB Register TcistmskmValue BT.656, Y/C Mode, or Raw Data Mode TCI M ode TCI System Time Clock Ticks Interrupt Register TciticksTickct 35. Video Capture Fifo Registers Function Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 34. Video Capture Fifo RegistersDisplaying Video in BT.656 or Y/C Mode Video Display Field and Frame OperationVideo Display Registers Recommended Values Image Timing Video Display Mode SelectionVideo Display Mode Selection Dmode Bits Mode DescriptionSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing Port Sync Operation Sync Signal GenerationBT.656 Video Display Mode External Sync OperationFpcount Vclkout Display Timing Reference Codes525/60 Description BT.656 Frame TimingLine Number Line NumberVclkout Blanking Codes3 BT.656 Image Display 4 BT.656 Fifo Unpacking3 Y/C Image Display Y/C Video Display Mode1 Y/C Display Timing Reference Codes 2 Y/C Blanking CodesOutput Filter Modes Output Filter Mode Selection4 Y/C Fifo Unpacking Video Output Filtering2x Co-Sited Scaling 15. Chrominance Re-sampling18. Output Edge Pixel Replication 2x Interspersed ScalingVertical Ancillary Vanc Data Display Raw Data Display ModeAncillary Data Display Horizontal Ancillary Hanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output SupportVdctl Bit Video Display Field and Frame OperationDisplay Determination and Notification Display OperationDisplay Line Boundary Conditions Video Display Event GenerationYfifo Display Timing ExamplesInterlaced BT.656 Timing Example Ipcount =IMGSIZE78Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout FlcountFrmwidth = IMGHOFF1 = 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display ExampleVclkin Fpcount Ipcount VCTL1 HblnkabVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example VCTL1 Hblnkac VCTL1 Hsyncac Vclkout Frmwidth = IMGHOFF1 = Hblnkstart =Hsyncstart = 1350 Hsyncstop = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing ExampleDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Registers Video Display Status Register VdstatVideo Display Control Registers Video Display Status Register Vdstat Field Descriptions Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions None Flddis Value BT.656 and Y/C Mode Raw Data ModeBlanking None FrmdisFrmwidth Video Display Frame Size Register VdfrmszVideo Display Horizontal Blanking Register Vdhblnk FrmheightField has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 ReservedVBLNKXSTOP1 VBLNKYSTOP1VBLNKXSTART2 VBLNKYSTART2VBLNKXSTOP2 Value BT.656 and Y/C ModeDEFAULT0 VBLNKYSTOP2None Negoff Video Display Field 1 Image Offset Register VDIMGOFF1IMGVOFF1 IMGHOFF1Video Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 IMGHSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2Video Display Field 1 Timing Register VDFLDT1 IMGVSIZE2FLD2YSTART Video Display Field 2 Timing Register VDFLDT2FLD1YSTART FLD1XSTARTVDTHRLD1 Video Display Threshold Register VdthrldVDTHRLD2 IncpixVideo Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCXSTOP1 VSYNCXSTART1VSYNCYSTART1 VSYNCYSTOP1VSYNCYSTART2 VSYNCXSTART2Crld Video Display Counter Reload Register VdreloadVrld Crld HrldDISPEVT1 Video Display Event Register VddispevtVideo Display Clipping Register Vdclip DISPEVT2Clipchigh Video Display Default Display Value Register VddefvalCrdefval Video Display Vertical Interrupt Register VdvintCrdefval Cbdefval Defval56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register VdfbitVBITSET1 FbitsetFbitclr VBITCLR1VBITSET2 VBITCLR2Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value 36. Video Display Fifo Registers Function Display ModeVideo Display Fifo Registers 35. Video Display Fifo RegistersGeneral-Purpose I/O Operation Gpio Registers Video Port RegistersOffset Address Acronym Register Name Class Video Port Peripheral Identification Register VppidType Class RevisionStop Video Port Peripheral Control Register PCRPeren Soft Free PerenVideo Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register PfuncNormal VDATA0TO9 Normal VDATA10TO19Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register PdirVDATA0T32IN VDATA0T32OUT VDATA12TO15IN VDATA12TO15OUTVDATA8TO9IN VDATA8TO9OUT VDATA4TO7IN VDATA4TO7OUTVideo Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register PdinPDOUT22 Video Port Pin Data Output Register PdoutVideo Port Pin Data Out Register Pdout Field Descriptions PDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register PdsetVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register PdclrVideo Port Pin Interrupt Enable Register Pien PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2PIEN22 Value Description Video Port Pin Interrupt Polarity Register PipolNone VCTL2INT Video Port Pin Interrupt Status Register PistatPISTAT22 None VCTL3INTVideo Port Pin Interrupt Clear Register Piclr PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2PICLR22 Vcxo Interpolated Control Port Interface VIC Port Interface SignalsVIC Port Signal Direction Description OverviewExample Values for Interpolation Rate Operational DetailsEnabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlVIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Products Applications DSPRfid