Texas Instruments TMS320DM648 manual Interlaced Raw Display Example

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Display Timing Examples

Figure 4-26. BT.656 Interlaced Display Vertical Timing Example

FLCOUNT

525

1

2

3

4

Field￿1￿blanking

5

6

	EAV
ILCOUNT	V	F
240	0	1
240	1	1
240	1	1
240	1	1
240	1	0
240	1	0
240	1	0

	AB	AB
FLD	VBLNK	VSYNC

Active

horizontal

output

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

19
20
21	Field￿1￿active
22
23
	Field￿1￿image
262
263
264
265
266
267
268	Field￿2￿blanking
269

282
283
284	Field￿2￿active
285
286
	Field￿2￿image
524
525
1

240	1	0
240	0	0
240	0	0
240	0	0

10 0

20 0

2390 0

2400 0

240	0	0
240	1	0
240	1	0
240	1	1
240	1	1
240	1	1
240	1	1
240	1	1
240	0	1
240	0	1
240	0	1
1	0	1

20 1

2390 0

2400 1

240	1	1
240	1	1

Blanking￿value

Default￿value§

Default￿value§

Default￿value§

FIFO￿data

FIFO￿data

FIFO￿data

FIFO￿data

Default￿value§

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Blanking￿value

Default￿value§

Default￿value§

Default￿value§

FIFO￿data

FIFO￿data

FIFO￿data

FIFO￿data

Blanking￿value

Blanking￿value

IMGVOFF1￿=￿3	VBLNKXSTART1￿=￿720	VSYNCXSTART1￿=￿720	FLD1XSTART =￿720
IMGVSIZE1￿=￿240	VBLNKYSTART1￿=￿1	VSYNCYSTART1￿=￿4	FLD1YSTART =￿1
IMGVOFF2￿=￿3	VBLNKXSTOP1￿-￿720	VSYNCXSTOP1￿=￿720	FLD2XSTART =￿360
IMGVSIZE2￿=￿240	VBLNKYSTOP1￿-￿20	VSYNCYSTOP1￿=￿7	FLD2YSTART =￿263
FRMHEIGHT =￿525	VBLNKXSTAR2￿=￿360	VSYNCXSTART2￿=￿360
VBITSET1￿=￿1	VBLNKYSTART2￿=￿263	VSYNCYSTART2￿=￿266	FBITSET =￿266
VBITCLR1￿=￿20	VBLNKXSTOP2￿=￿360	VSYNCXSTOP2￿=￿360	FBITCLR￿=￿4
VBITSET2￿=￿264	BLNKYSTOP2￿=￿283	VSYNCYSTOP2￿=￿269
VBITCLR2￿=￿283

AAssumes VCT1P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK output when VCTL2S bit is set 01.

BIf DVEN bit in VDCTL is set to 1; otherwise, blanking value is output.

4.9.2Interlaced Raw Display Example

This section shows an example of raw display output for the same 704 x 408 interlaced image.

The horizontal output timing is shown in Figure 4-27. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins. The actual delay can be longer or shorter as long as it is consistent within any display mode. The active line is 720-pixels wide. Figure 4-27shows the 704-pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels.

The HBLNK and HSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally. The HBLNK inactive edge occurs on sample 0.

The IPCOUNT operation follows the description in Section 4.1.2. IPCOUNT resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). Both the IPCOUNT and FPCOUNT counters increment on every third VCLKIN rising edge, as programmed by the INCPIX bits in VDTHRLD with a value of 3.

VDOUT shows the output data and switching between Default Data, and FIFO Data. Three values are output sequentially on VDOUT for each pixel count. Note that the default value is output during both the blanking and non-display image active video regions.

SPRUEM1 –May 2007 Video Display Port 113

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