Texas Instruments TMS320DM648 manual BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved

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Video Display Registers

Figure 4-34. Video Display Horizontal Blanking Register (VDHBLNK)

31		28	27	16
	Reserved			HBLNKSTOP
	R-0			R/W-0
15	14	12	11	0
HBDLA	Reserved			HBLNKSTART
R/W-0	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 4-9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions

					Description
Bit	field (1)	symval (1)	Value	BT.656 and Y/C Mode	Raw Data Mode
31-28	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
				field has no effect.

27-16	HBLNKSTOP	OF(value)	0-FFFh	Location of SAV code and HBLNK
				inactive edge within the line. HBLNK
				inactive edge may be optionally
				delayed by 4 VCLKs.
		DEFAULT	0
15	HBDLA	OF(value)		Horizontal blanking delay enable bit.
		DEFAULT	0	Horizontal blanking delay is disabled.
		NONE
		DELAY	1	HBLNK inactive edge is delayed by 4
				VCLKs.

Ending pixel (FPCOUNT) of blanking video area (HBLNK inactive) within the line.

Not used.

Not used.

14-12 Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this
			field has no effect.

11-0 HBLNKSTART	OF(value)	0-FFFh Location of EAV code and HBLNK
		active edge within the line.
	DEFAULT	0

Starting pixel (FPCOUNT) of blanking video area (HBLNK active) within the line.

(1)For CSL implementation, use the notation VP_VDHBLNK_field_symval

4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)

In raw data mode, VBLNK is asserted whenever the frame line counter (FLCOUNT) is equal to VBLNKYSTART1 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTART1 (this is shown in Figure 4-6).

In BT.656 and Y/C mode, VBLNK is asserted whenever FLCOUNT = VBLNKYSTART1 and FPCOUNT = VBLNKXSTART1. This VBLNK output control is completely independent of the timing control codes. The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.

The video display field 1 vertical blanking start register (VDVBLKS1) controls the start of vertical blanking in field 1.

The video display field 1 vertical blanking start register (VDVBLKS1) is shown in Figure 4-35and described in Table 4-10.

128 Video Display Port SPRUEM1 –May 2007

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