Texas Instruments TMS320DM648 manual TCI System Time Clock Compare LSB Register Tcistcmpl, Atc

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Video Capture Registers

3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL)

The transport stream interface system time clock compare LSB register (TCISTCMPL) is used to generate an interrupt at some absolute time based on the STC. TCISTCMPL holds the 32 least-significant bits (LSBs) of the absolute time compare (ATC). Whenever the value in TCISTCMPL and TCISTCMPM match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TCICTL is set, the STC bit in VPIS is set. .

To prevent inaccurate comparisons caused by changing register bits, the software should disable the system time clock interrupt (clear the STEN bit in TCICTL) prior to writing to TCISTCMPL.

The TCI system time clock compare LSB register (TCISTCMPL) is shown in Figure 3-36and described in Table 3-29

Figure 3-36. TCI System Time Clock Compare LSB Register (TCISTCMPL)

31 0

ATC

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 3-29. TCI System Time Clock Compare LSB Register (TCISTCMPL) Field Descriptions

				Description
Bit	field	symval (1)	Value	BT.656, Y/C Mode, or Raw Data Mode	TCI Mode
31-0	ATC	OF(value)	0-FFFF FFFFh	Not used.	Contains the 32 LSBs of the absolute
					time compare.
		DEFAULT	0

(1)For CSL implementation, use the notation VP_TCISTCMPL_ATC_symval

3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM)

The transport stream interface system time clock compare MSB register (TCISTCMPM) is used to generate an interrupt at some absolute time based on the STC. TCISTCMPM holds the most-significant bit (MSB) of the absolute time compare (ATC). Whenever the value in TCISTCMPM and TCISTCMPL match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TCICTL is set, the STC bit in VPIS is set. .

To prevent inaccurate comparisons caused by changing register bits, the software should disable the system time clock interrupt (clear the STEN bit in TCICTL) prior to writing to TCISTCMPM.

The TCI system time clock compare MSB register (TCISTCMPM) is shown in Figure 3-37and described in Table 3-30

Figure 3-37. TCI System Time Clock Compare MSB Register (TCISTCMPM)

31		16
Reserved
R-0
15	1	0
Reserved		ATC
R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

88	Video Capture Port	SPRUEM1 –May 2007
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