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Texas Instruments TMS320DM648 manual 3 Y/C Progressive Display Example

Models: TMS320DM648

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Display Timing Examples

4.9.3 Y/C Progressive Display Example

This section shows an example of progressive display operation. The output format follows SMPTE

296M-2001 specifications for a 1280 x 720/60 system. The example is for a 1264 x 716 progressive output image.

The horizontal output timing is shown in Figure 4-29. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins. The actual delay can be longer or shorter as long as it is consistent within any display mode. The SMPTE 296M 60-Hz active line is 1650-pixels wide. Figure 4-29shows the 1264-pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels.

The HBLNK and HSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally. The HBLNK inactive edge occurs either on sample 1646 coincident with the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true SMPTE 296M operation, neither HBLNK nor HSYNC would be used.

The IPCOUNT operation follows the description in Section 4.1.2. IPCOUNT resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). The operation during non-display time is not a requirement, it could continue counting until the next FPCOUNT = IMGHOFFx point or it could reset immediately after IMGHSIZEx or when FPCOUNT is reset.

VDOUT shows the output data and switching between EAV, Blanking Data, SAV, Default Data, and FIFO Data. It is assumed that the DVEN bit in VDCTL is set to enable the default output.

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Video Display Port

SPRUEM1 –May 2007

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Texas Instruments TMS320DM648 manual 3 Y/C Progressive Display Example

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Related Documentation From Texas Instruments About This ManualNotational Conventions Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Video Port Fifo Edma InterfaceVideo Capture Fifo Configurations BT.656 Video Capture Fifo ConfigurationYsrca Y/C Video Capture Fifo Configuration Video Display Fifo Configurations Bit Raw Video Capture Fifo ConfigurationBit Locked Raw Video Display Fifo Configuration 10. Y/C Video Display Fifo Configuration Video Port RegistersVideo Port Pin Mapping Video Capture Signal Mapping1Video Display Signal Mapping Vdin Data Bus Usage for Capture Modes1 Capture Mode BT.656 Raw Data Data Bus BitVdin Bus Usage for Capture Modes Vdout Data Bus Usage for Display Modes Video Port Pin MultiplexingVideoPort Clocking Vdout Data Bus Usage for Display Modes1Video Port Reset Operation Power-On ResetPeripheral Bus Reset Software Port ResetInterrupt Operation Capture Channel ResetDisplay Channel Reset Edma Operation Capture Edma Event GenerationDisplay Edma Event Generation Edma Size and Threshold RestrictionsEdma Interface Operation Video Port Control RegistersVideo Port Control Registers Acronym Register NameDescription Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Video Port Operating Mode Selection Operating ModeVideo Port Status Register Vpstat Video Port Status Register Vpstat Field DescriptionsVideo Port Interrupt Enable Register Vpie Dcna LfdaVideo Port Interrupt Status Register Vpis Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVideo Port Interrupt Status Register Vpis Field Descriptions None Clear VdctlShort field detected on channel a interrupt detected bit Covra BT.656 and Y/C Mode Field and Frame Operation Video Capture PortVideo Capture Mode Selection BT.656 Video Capture ModeVideo Capture Mode Selection 1 BT.656 Capture ChannelsError Correction by Protection Bits BT.656 Protection Bits3 BT.656 Image Window and Capture Video Capture Parameters4 BT.656 Data Sampling 5 BT.656 Fifo PackingCommon Video Source Parameters Video SourceY/C Video Capture Mode 1 Y/C Capture Channels2 Y/C Timing Reference Codes 3 Y/C Image Window and CaptureBT.656 and Y/C Mode Field and Frame Operation 4 Y/C Fifo PackingBit Y/C Fifo Packing VclkinaBT.656 and Y/C Mode Capture Operation Capture Determination and NotificationVC xCTL Bit OperationVertical Counter Reset Point Vertical SynchronizationVertical Synchronization Programming EAVVcount Operation Example EXC = VRST=0 VRST=1 FINV=0 FINV=1 VcountHorizontal Counter Reset Point Horizontal SynchronizationHorizontal Synchronization Programming VCxCTL BitField Detect Method Field IdentificationField Identification Programming Short and Long Field Detect Video Input FilteringVclkin VSYNC# VCTL2 HSYNC# VCTL110. Input Filter Mode Selection Input Filter ModesChrominance Re-sampling Operation Scaling OperationEdge Pixel Replication 2 Scaled Co-Sited FilteringAncillary Data Capture 11. Edge Pixel ReplicationRaw Data Capture Mode Horizontal Ancillary Hanc Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture NotificationFrmc 11. Raw Data Mode Capture OperationRaw Data Fifo Packing TCI Data Capture TCI Capture ModeTCI Capture Features PCR TCI Capture Error DetectionSynchronizing the System Clock 12. TCI Capture Mode Operation TCI Data Capture NotificationVcactl Bit Clear FrmcPerr Psterr Writing to the FifoReading from the Fifo Capturing Video in BT.656 or Y/C Mode Capture Line Boundary ConditionsHandling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data ModeHandling Fifo Overrun Condition in Raw Data Mode Capturing Data in TCI Capture Mode13. Video Capture Control Registers Handling Fifo Overrun Condition in TCI Capture ModeVideo Capture Registers Vcfld Vcxpos Video Capture Channel x Status Register VCASTAT, VcbstatFsync Frmc F2C F1C Vcypos Description Bit BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel a Control Register Vcactl None Reset Rstch BlkcapRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde ResmplEavsav Extern Eavfid FDLV1EAV V0EAVValue BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Start Register VCxSTRT1Video Capture Channel x Field 1 Stop Register VCxSTOP1 Vcxstop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcystop Video Capture Channel x Field 2 Stop Register VCxSTOP2 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD2 VCTHRLD1Video Capture Channel x Event Count Register VCxEVTCT Video Capture Channel B Control Register VcbctlCAPEVTCT2 CAPEVTCT130. Video Capture Channel B Control Register Vcbctl Vrst Hrst VcenSAV or VCTL1 inactive edge Not used 24. TCI Capture Control Register Tcictl Field Descriptions BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI Capture Control Register Tcictl TCI Clock Initialization LSB Register Tciclkinitl InpcrTCI System Time Clock LSB Register Tcistclkl Bit Value ModeTCI Clock Initialization MSB Register Tciclkinitm Default Pcrm TCI System Time Clock MSB Register TcistclkmPcre Pcrm PcreATC TCI System Time Clock Compare LSB Register TcistcmplTCI System Time Clock Compare MSB Register Tcistcmpm Value BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI System Time Clock Compare Mask LSB Register TcistmsklTCI System Time Clock Compare Mask MSB Register Tcistmskm AtcmTickct Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTCI System Time Clock Ticks Interrupt Register Tciticks Capture Mode Register BT.656 or Y/C Raw Data Video Capture Fifo Registers34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Registers Recommended Values Displaying Video in BT.656 or Y/C ModeVideo Display Field and Frame Operation Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video AreaHorizontal Blanking and Horizontal Sync Timing Sync Signal Generation BT.656 Video Display ModeExternal Sync Operation Port Sync OperationDisplay Timing Reference Codes Fpcount VclkoutBT.656 Frame Timing Line NumberLine Number 525/60 DescriptionBlanking Codes 3 BT.656 Image Display4 BT.656 Fifo Unpacking VclkoutY/C Video Display Mode 1 Y/C Display Timing Reference Codes2 Y/C Blanking Codes 3 Y/C Image DisplayOutput Filter Mode Selection 4 Y/C Fifo UnpackingVideo Output Filtering Output Filter Modes15. Chrominance Re-sampling 2x Co-Sited Scaling2x Interspersed Scaling 18. Output Edge Pixel ReplicationRaw Data Display Mode Ancillary Data DisplayHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Mode RGB Output Support Raw Data Fifo UnpackingVideo Display Field and Frame Operation Display Determination and NotificationDisplay Operation Vdctl BitVideo Display Event Generation Display Line Boundary ConditionsDisplay Timing Examples Interlaced BT.656 Timing ExampleIpcount =IMGSIZE78 YfifoFrmwidth = IMGHOFF1 = Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFlcount 112 Interlaced Raw Display Example 26. BT.656 Interlaced Display Vertical Timing ExampleVCTL1 Hsyncab Vclkout Vclkin FpcountIpcount VCTL1 Hblnkab 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Hsyncstart = 1350 Hsyncstop = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = Hblnkstart = 30. Y/C Progressive Display Vertical Timing Example Flcount EAV Ilcount V FDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Control Register Vdctl Video Display Status Register Vdstat Field DescriptionsBT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field DescriptionsVideo Display Control Register Vdctl Field Descriptions Value BT.656 and Y/C Mode Raw Data Mode BlankingNone Frmdis None FlddisVideo Display Frame Size Register Vdfrmsz Video Display Horizontal Blanking Register VdhblnkFrmheight FrmwidthBT.656 and Y/C Mode Raw Data Mode 31-28 Reserved Field has no effectVBLNKYSTOP1 VBLNKXSTOP1VBLNKYSTART2 VBLNKXSTART2Value BT.656 and Y/C Mode DEFAULT0VBLNKYSTOP2 VBLNKXSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGVOFF1IMGHOFF1 None NegoffIMGHSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGVSIZE1 IMGHOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGVOFF2 Video Display Field 2 Image Size Register VDIMGSZ2 Video Display Field 1 Timing Register VDFLDT1IMGVSIZE2 IMGHSIZE2Video Display Field 2 Timing Register VDFLDT2 FLD1YSTARTFLD1XSTART FLD2YSTARTVideo Display Threshold Register Vdthrld VDTHRLD2Incpix VDTHRLD1Hsyncstart Video Display Horizontal Synchronization Register VdhsyncHsyncstop VSYNCXSTART1 VSYNCYSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCXSTART2 VSYNCYSTART2Video Display Counter Reload Register Vdreload VrldCrld Hrld CrldVideo Display Event Register Vddispevt Video Display Clipping Register VdclipDISPEVT2 DISPEVT1Video Display Default Display Value Register Vddefval ClipchighVideo Display Vertical Interrupt Register Vdvint Crdefval CbdefvalDefval CrdefvalVideo Display Field Bit Register Vdfbit 56. Video Display Vertical Interrupt Register VdvintFbitset FbitclrVBITCLR1 VBITSET1VBITCLR2 VBITSET2Register Field 525/60 Value Video Display Registers Recommended Values34. Video Display Register Recommended Values Display Mode Video Display Fifo Registers35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGeneral-Purpose I/O Operation Offset Address Acronym Register Name Gpio RegistersVideo Port Registers Video Port Peripheral Identification Register Vppid TypeClass Revision ClassVideo Port Peripheral Control Register PCR Peren Soft FreePeren StopVideo Port Pin Function Register Pfunc Video Port Pin Function Register Pfunc Field DescriptionsNormal VDATA10TO19 Normal VDATA0TO9Video Port Pin Direction Register Pdir Video Port Pin Direction Register Pdir Field DescriptionsVDATA12TO15IN VDATA12TO15OUT VDATA8TO9IN VDATA8TO9OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUTVideo Port Pin Data Input Register Pdin Video Port Pin Data Input Register Pdin Field DescriptionsVideo Port Pin Data Output Register Pdout Video Port Pin Data Out Register Pdout Field DescriptionsPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field DescriptionsVideo Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register Pdclr Field DescriptionsPIEN22 Video Port Pin Interrupt Enable Register PienPIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Video Port Pin Interrupt Polarity Register Pipol Value DescriptionVideo Port Pin Interrupt Status Register Pistat PISTAT22None VCTL3INT None VCTL2INTPICLR22 Video Port Pin Interrupt Clear Register PiclrPICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Vcxo Interpolated Control Port VIC Port Interface Signals VIC Port Signal Direction DescriptionOverview InterfaceOperational Details Example Values for Interpolation RateVIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field DescriptionsVicinbits VIC Input Register VicinVIC Input Register Vicin Field Descriptions Vicclkdiv VIC Clock Divider Register VicdivVIC Clock Divider Register Vicdiv Field Descriptions Rfid Products ApplicationsDSP