Texas Instruments TMS320DM648 manual Ysrca

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Video Port FIFO

For 8-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1-3. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus. Each channel'sFIFO has a separate write pointer and read register (YSRCx). The FIFO configuration is identical for TCI capture, but channel B is disabled.

Figure 1-3. 8-Bit Raw Video Capture and TCI Video Capture FIFO Configuration

Capture FIFO A

VDIN[9−2]

8

64

YSRCA

Buffer A (2560 bytes)

Capture FIFO B

VDIN[19−12]

8

64

YSRCB

Buffer B (2560 bytes)

SPRUEM1 –May 2007 Overview 21

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