Texas Instruments TMS320DM648 manual Video Port Status Register Vpstat

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Video Port Control Registers

2.4.2 Video Port Status Register (VPSTAT)

The video port status register (VPSTAT) indicates the current condition of the video port. The video port status register (VPSTAT) is shown in Figure 2-2and described in Table 2-4.

Figure 2-2. Video Port Status Register (VPSTAT)

31					16
	Reserved
	R-0
15	4	3	2	1	0
Reserved		DCDIS	HIDATA	Reserved
R-0		R-x	R-x		R-0

LEGEND: R = Read only; -n= value after reset

Table 2-4. Video Port Status Register (VPSTAT) Field Descriptions

Bit	field (1)	symval (1)	Value	Description
31-4	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
3	DCDIS	OF(value)		Dual-channel disable bit. The default value is determined by the chip-level
				configuration.
		DEFAULT	0	Dual-channel operation is enabled.
		ENABLE
		DISABLE	1	Port muxing selections prevent dual-channel operation.
2	HIDATA	OF(value)		High data bus half. HIDATA does not affect video port operation but is provided to
				inform you which VDATA pins may be controlled by the video port GPIO registers.
				HIDATA is never set unless DCDIS is also set. The default value is determined by the
				chip-level configuration.
		DEFAULT	0
		NONE
		USE	1	Indicates that another peripheral is using VDATA[9-2] and the video port channel A
				(VDIN[9-2] or VDOUT[9-2]) is muxed onto VDATA[19-12].
1-0	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.

(1)For CSL implementation, use the notation VP_VPSTAT_field_symval

SPRUEM1 –May 2007	Video Port	37
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