Texas Instruments TMS320DM648 manual Handling Under-run Condition of the Display Fifo

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Displaying Video in Raw Data Mode

by total double words per Y EDMA.

20.Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired.

21.Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and the FPCOUNT increment rate (INCPIX bit).

22.Write to VDCTL to:

∙Set display mode (DMODE =01x for 8-bit output, 11x for 16 bit output).

∙Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).

∙Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external sync inputs (HXS, VXS, FXS bits).

∙Select 10-bit unpacking mode (DPK bit), if appropriate.

∙Set VDEN bit to enable the display.

23.Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized.

∙In VPIE, poll for display complete (DCMP) interrupts.

∙Write to clear DCMP.

∙Poll for DCMP again.

∙Write to clear DCMP again.

24.Write to VDCTL to clear the BLKDIS bit.

25.Set the video display field 1 timing. Specify the first line and pixel of field 1 in VDFLDT1.

26.Display is enabled at the start of the first frame after BLKDIS = 0 and begins with the first selected field. EDMA events are generated as triggered by VDTHRLD and the DEVTCT counter. When a selected field has been displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH), the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is enabled in VPIE.

27.If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output.

4.11.1Handling Under-run Condition of the Display FIFO

A FIFO under-run occurs when the display FIFO is empty during an active display line because a pending EDMA request failed to load the data in time. In case of a FIFO under-run condition, the DUND bit in VPIS is set. This condition initiates an interrupt to the DSP, if the under-run interrupt is enabled (the DUND bit in VPIE is set).

Because video display is typically a continuous real-time output, data output is not halted when a FIFO under-run occurs. (To output a blanking of default value is just as catastrophic to a display as outputting an old data value.) Instead, the FIFO read pointer continues to advance and (old) data continues to be output from the FIFO. This means that if the pending EDMA is only slightly late, the data transfer has a chance to catch the FIFO back up to the read pointer and correct data output resumes. If the pending EDMA does not complete service within a threshold'sworth of output data, then the EDMA request sequence is broken and the remainder of the display field is corrupted.

The under-run interrupt routine should set the BLKDIS bit in VDCTL and it should reconfigure the EDMA channel settings. Setting the BLKDIS bit flushes the channel display FIFO and prevents channel EDMA events from reaching the EDMA controller. The EDMA must be reconfigured correctly for the next frame display since the current frame transfer failed. The frame line and frame pixel counters continue counting and, from a pin standpoint, the video display module appears to continue to function normally (SAV/EAV codes are generated in the BT.656 or Y/C mode and the default data value is sent out). The BLKDIS bit should then be cleared to reenable EDMA events. Clearing the BLKDIS bit does not enable EDMA events during the frame where the bit is cleared. Clearing this bit to zero enables EDMA events in the frame that follows the frame where the bit is cleared.

SPRUEM1 –May 2007 Video Display Port 121

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