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Capturing Video in Raw Data Mode
number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx, CbEVTx, and CrEVTx are generated by the video capture module.
7.Configure an EDMA channel to move data from YSRCx to a destination in the DSP memory. The channel transfers should be triggered by the YEVTx. The size of the transfers should be set appropriately during the configuration of the EDMA channel parameters. The EDMA must start on a double word boundary and move an even number of words.
8.Configure a EDMA channel to move data from CBSRCx to a destination in the DSP memory. The channel transfers should be triggered by the CbEVTx. The size of the transfers should be set appropriately during the configuration of the EDMA channel parameters. The EDMA must start on a double word boundary and move an even number of words.
9.Configure a EDMA channel to move data from CRSRCx to a destination in the DSP memory. The channel transfers should be triggered by the CrEVTx. The size of the transfers should be set appropriately during the configuration of the EDMA channel parameters. The EDMA must start on a
10.Write to the video port interrupt enable register (VPIE) to enable overrun (COVRx) and capture complete (CCMPx) interrupts, if desired.
11.Write to VCxCTL to:
∙Set capture mode (CMODE = 0x0 for BT.656 input, 0x4 for Y/C input).
∙Set desired field/frame operation (CON, FRAME, CF2, CF1 bits).
∙Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits).
∙Enable scaling (SCALE and RESMPL bits), if desired and using
∙Set VCEN bit to enable capture.
12.Capture is enabled at the start of the first frame after VCEN = 1 and begins at the start of the first selected field. EDMA events are generated as triggered by VCxTHRLDx. When a selected field has been captured (VCXPOS = VCXSTOP and VCYPOS = VCYSTOP), the F1C, F2C, or FRMC bits in VCxSTAT are set and cause the CCMPx bit in VPIS to be set. This generates a DSP interrupt, if the CCMPx bit is enabled in VPIE.
13.If continuous capture is enabled, the video port begins capturing again at the start of the next selected field or frame. If noncontinuous field 1 and field 2 or frame capture is enabled, the next field or frame is captured, during which the DSP must clear the appropriate completion status bit or further capture is disabled. If single frame capture is enabled, capture is disabled until the DSP clears the FRMC bit.
3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVR bit in VPIE enables overrun interrupt).
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure EDMA channel settings. The EDMA channel must be reconfigured for capture of the next frame since the current frame transfer failed. Setting the BLKCAP bit flushes the capture FIFO and blocks EDMA events for the channel. As long as the BLKCAP bit is set, the video capture channel ignores the incoming data with exception of SAV and EAV codes but the internal counters continue counting.
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing the BLKCAP bit takes effect in the subsequent video field (EDMA events are still going to be blocked in the video field in which the BLKCAP bit is cleared.)
3.11 Capturing Video in Raw Data Mode
In order to capture video in the raw data mode, the following steps are needed:
1.To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that the multiplexed pins work as Video Port Pins. Refer to the
2.Program the VPx_CTL Register appropriately to use the desired Video Port as a Capture Port.
3.Set the PEREN bit in the video port peripheral control register (PCR).
4.Set VCxSTOP1 to specify size of an image to be captured (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured image size in bytes).
68 | Video Capture Port | SPRUEM1 |
