Texas Instruments TMS320DM648 specification

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GPIO Registers

5.1.8 Video Port Pin Data Clear Register (PDCLR)

PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s.

The video port pin data clear register (PDCLR) is shown in Figure 5-8and described in Table 5-9.

Figure 5-8. Video Port Pin Data Clear Register (PDCLR)

31							24
			Reserved
				R-0
23	22	21	20	19	18	17	16
Reserved	PDCLR22	PDCLR21	PDCLR20	PDCLR19	PDCLR18	PDCLR17	PDCLR16
R-0	W-0	W-0	W-0	W-0	W-0	W-0	W-0
15	14	13	12	11	10	9	8
PDCLR15	PDCLR14	PDCLR13	PDCLR12	Reserved	Reserved	PDCLR9	PDCLR8
W-0	W-0	W-0	W-0	W-0	W-0	W-0	W-0
7	6	5	4	3	2	1	0
PDCLR7	PDCLR6	PDCLR5	PDCLR4	PDCLR3	PDCLR2	Reserved	Reserved
W-0	W-0	W-0	W-0	W-0	W-0	R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5-9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions

Bit	field (1)	symval (1)	Value	Description
31-23	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
22	PDCLR22	OF(value)		Allows PDOUT22 bit to be cleared to a logic low without affecting other I/O pins
				controlled by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL3CLR	1	Clears PDOUT22 (VCTL3) bit to 0.
21	PDCLR21	OF(value)		Allows PDOUT21 bit to be cleared to a logic low without affecting other I/O pins
				controlled by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL2CLR	1	Clears PDOUT21 (VCTL2) bit to 0.
20	PDCLR20	OF(value)		Allows PDOUT20 bit to be cleared to a logic low without affecting other I/O pins
				controlled by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL1CLR	1	Clears PDOUT20 (VCTL1) bit to 0.
19-2	PDCLR[19-2]	OF(value)		Allows PDOUT[19-2] bit to be cleared to a logic low without affecting other I/O pins
				controlled by the same port.
		DEFAULT	0	No effect.
		NONE
		VDATAnCLR	1	Clears PDOUT[n] (VDATA[n]) bit to 0.

(1)For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval

162

General-Purpose I/O Operation

SPRUEM1 –May 2007

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Texas Instruments TMS320DM648 manual Video Port Pin Data Clear Register Pdclr

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values About This Manual Notational ConventionsRelated Documentation From Texas Instruments Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Video Port Fifo Edma Interface Video Capture Fifo Configurations BT.656 Video Capture Fifo Configuration Ysrca Y/C Video Capture Fifo Configuration Video Display Fifo Configurations Bit Raw Video Capture Fifo Configuration Bit Locked Raw Video Display Fifo Configuration 10. Y/C Video Display Fifo Configuration Video Port Registers Video Capture Signal Mapping1 Video Display Signal MappingVideo Port Pin Mapping Capture Mode BT.656 Raw Data Data Bus Bit Vdin Bus Usage for Capture ModesVdin Data Bus Usage for Capture Modes1 VideoPort Clocking Vdout Data Bus Usage for Display ModesVideo Port Pin Multiplexing Vdout Data Bus Usage for Display Modes1 Video Port Peripheral Bus Reset Reset OperationPower-On Reset Software Port Reset Capture Channel Reset Display Channel ResetInterrupt Operation Edma Operation Capture Edma Event Generation Display Edma Event Generation Edma Size and Threshold Restrictions Video Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register Name Video Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsDescription Video Port Operating Mode Selection Operating Mode Video Port Status Register Vpstat Video Port Status Register Vpstat Field Descriptions Video Port Interrupt Enable Register Vpie Dcna Lfda Video Port Interrupt Status Register Vpis Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register Vpis Field Descriptions None Clear Vdctl Short field detected on channel a interrupt detected bit Covra BT.656 and Y/C Mode Field and Frame Operation Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionBT.656 Video Capture Mode 1 BT.656 Capture Channels Error Correction by Protection Bits BT.656 Protection Bits 3 BT.656 Image Window and Capture Video Capture Parameters Common Video Source Parameters 4 BT.656 Data Sampling5 BT.656 Fifo Packing Video Source 2 Y/C Timing Reference Codes Y/C Video Capture Mode1 Y/C Capture Channels 3 Y/C Image Window and Capture Bit Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame Operation4 Y/C Fifo Packing Vclkina VC xCTL Bit BT.656 and Y/C Mode Capture OperationCapture Determination and Notification Operation Vertical Synchronization Programming Vertical Counter Reset PointVertical Synchronization EAV Vcount Operation Example EXC = VRST=0 VRST=1 FINV=0 FINV=1 Vcount Horizontal Synchronization Programming Horizontal Counter Reset PointHorizontal Synchronization VCxCTL Bit Field Identification Field Identification ProgrammingField Detect Method Vclkin VSYNC# VCTL2 Short and Long Field DetectVideo Input Filtering HSYNC# VCTL1 Chrominance Re-sampling Operation 10. Input Filter Mode SelectionInput Filter Modes Scaling Operation Edge Pixel Replication 2 Scaled Co-Sited Filtering Ancillary Data Capture 11. Edge Pixel Replication Vertical Ancillary Vanc Data Capture Raw Data Capture ModeHorizontal Ancillary Hanc Data Capture Raw Data Capture Notification 11. Raw Data Mode Capture Operation Raw Data Fifo PackingFrmc TCI Capture Mode TCI Capture FeaturesTCI Data Capture TCI Capture Error Detection Synchronizing the System ClockPCR Vcactl Bit 12. TCI Capture Mode OperationTCI Data Capture Notification Clear Frmc Writing to the Fifo Reading from the FifoPerr Psterr Capturing Video in BT.656 or Y/C Mode Capture Line Boundary Conditions Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun Condition in Raw Data Mode Capturing Data in TCI Capture Mode Handling Fifo Overrun Condition in TCI Capture Mode Video Capture Registers13. Video Capture Control Registers Video Capture Channel x Status Register VCASTAT, Vcbstat Fsync Frmc F2C F1C VcyposVcfld Vcxpos BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel a Control Register VcactlDescription Bit Rdfe Finv EXC Fldd Vrst Hrst Vcen None ResetRstch Blkcap Lfde Sfde Resmpl V1EAV Eavsav ExternEavfid FDL V0EAV Value BT.656 or Y/C Mode Raw Data Mode TCI Mode Video Capture Channel x Field 1 Start Register VCxSTRT1 Video Capture Channel x Field 1 Stop Register VCxSTOP1 Video Capture Channel x Field 2 Start Register VCxSTRT2 VcystopVcxstop Video Capture Channel x Field 2 Stop Register VCxSTOP2 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD2 VCTHRLD1 CAPEVTCT2 Video Capture Channel x Event Count Register VCxEVTCTVideo Capture Channel B Control Register Vcbctl CAPEVTCT1 30. Video Capture Channel B Control Register Vcbctl Vrst Hrst Vcen SAV or VCTL1 inactive edge Not used BT.656, Y/C Mode, or Raw Data Mode TCI Mode TCI Capture Control Register Tcictl24. TCI Capture Control Register Tcictl Field Descriptions TCI Clock Initialization LSB Register Tciclkinitl Inpcr Bit Value Mode TCI Clock Initialization MSB Register TciclkinitmTCI System Time Clock LSB Register Tcistclkl Pcre Pcrm Default PcrmTCI System Time Clock MSB Register Tcistclkm Pcre TCI System Time Clock Compare LSB Register Tcistcmpl TCI System Time Clock Compare MSB Register TcistcmpmATC TCI System Time Clock Compare Mask MSB Register Tcistmskm Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask LSB Register Tcistmskl Atcm Value BT.656, Y/C Mode, or Raw Data Mode TCI M ode TCI System Time Clock Ticks Interrupt Register TciticksTickct 34. Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 35. Video Capture Fifo Registers Function Displaying Video in BT.656 or Y/C Mode Video Display Field and Frame OperationVideo Display Registers Recommended Values Dmode Bits Mode Description Video Display Mode SelectionVideo Display Mode Selection Image Timing Smpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video Area Horizontal Blanking and Horizontal Sync Timing External Sync Operation Sync Signal GenerationBT.656 Video Display Mode Port Sync Operation Display Timing Reference Codes Fpcount Vclkout Line Number BT.656 Frame TimingLine Number 525/60 Description 4 BT.656 Fifo Unpacking Blanking Codes3 BT.656 Image Display Vclkout 2 Y/C Blanking Codes Y/C Video Display Mode1 Y/C Display Timing Reference Codes 3 Y/C Image Display Video Output Filtering Output Filter Mode Selection4 Y/C Fifo Unpacking Output Filter Modes 15. Chrominance Re-sampling 2x Co-Sited Scaling 2x Interspersed Scaling 18. Output Edge Pixel Replication Horizontal Ancillary Hanc Data Display Raw Data Display ModeAncillary Data Display Vertical Ancillary Vanc Data Display Raw Mode RGB Output Support Raw Data Fifo Unpacking Display Operation Video Display Field and Frame OperationDisplay Determination and Notification Vdctl Bit Video Display Event Generation Display Line Boundary Conditions Ipcount =IMGSIZE78 Display Timing ExamplesInterlaced BT.656 Timing Example Yfifo Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac Vclkout FlcountFrmwidth = IMGHOFF1 = 112 Interlaced Raw Display Example 26. BT.656 Interlaced Display Vertical Timing Example Vclkin Fpcount Ipcount VCTL1 HblnkabVCTL1 Hsyncab Vclkout 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example VCTL1 Hblnkac VCTL1 Hsyncac Vclkout Frmwidth = IMGHOFF1 = Hblnkstart =Hsyncstart = 1350 Hsyncstop = 30. Y/C Progressive Display Vertical Timing Example Flcount EAV Ilcount V F Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Registers Video Display Status Register VdstatVideo Display Control Registers Video Display Control Register Vdctl Video Display Status Register Vdstat Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register Vdctl Field Descriptions Video Display Control Register Vdctl Field Descriptions None Frmdis Value BT.656 and Y/C Mode Raw Data ModeBlanking None Flddis Frmheight Video Display Frame Size Register VdfrmszVideo Display Horizontal Blanking Register Vdhblnk Frmwidth BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved Field has no effect VBLNKYSTOP1 VBLNKXSTOP1 VBLNKYSTART2 VBLNKXSTART2 VBLNKYSTOP2 Value BT.656 and Y/C ModeDEFAULT0 VBLNKXSTOP2 IMGHOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGVOFF1 None Negoff Video Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 IMGVSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2Video Display Field 1 Timing Register VDFLDT1 IMGHSIZE2 FLD1XSTART Video Display Field 2 Timing Register VDFLDT2FLD1YSTART FLD2YSTART Incpix Video Display Threshold Register VdthrldVDTHRLD2 VDTHRLD1 Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCYSTOP1 VSYNCXSTART1VSYNCYSTART1 VSYNCXSTOP1 VSYNCXSTART2 VSYNCYSTART2 Crld Hrld Video Display Counter Reload Register VdreloadVrld Crld DISPEVT2 Video Display Event Register VddispevtVideo Display Clipping Register Vdclip DISPEVT1 Video Display Default Display Value Register Vddefval Clipchigh Defval Video Display Vertical Interrupt Register VdvintCrdefval Cbdefval Crdefval Video Display Field Bit Register Vdfbit 56. Video Display Vertical Interrupt Register Vdvint VBITCLR1 FbitsetFbitclr VBITSET1 VBITCLR2 VBITSET2 Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value 35. Video Display Fifo Registers Display ModeVideo Display Fifo Registers 36. Video Display Fifo Registers Function General-Purpose I/O Operation Gpio Registers Video Port RegistersOffset Address Acronym Register Name Class Revision Video Port Peripheral Identification Register VppidType Class Peren Video Port Peripheral Control Register PCRPeren Soft Free Stop Video Port Pin Function Register Pfunc Video Port Pin Function Register Pfunc Field Descriptions Normal VDATA10TO19 Normal VDATA0TO9 Video Port Pin Direction Register Pdir Video Port Pin Direction Register Pdir Field Descriptions VDATA4TO7IN VDATA4TO7OUT VDATA12TO15IN VDATA12TO15OUTVDATA8TO9IN VDATA8TO9OUT VDATA0T32IN VDATA0T32OUT Video Port Pin Data Input Register Pdin Video Port Pin Data Input Register Pdin Field Descriptions PDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 Video Port Pin Data Output Register PdoutVideo Port Pin Data Out Register Pdout Field Descriptions PDOUT22 When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien PIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2PIEN22 Video Port Pin Interrupt Polarity Register Pipol Value Description None VCTL3INT Video Port Pin Interrupt Status Register PistatPISTAT22 None VCTL2INT Video Port Pin Interrupt Clear Register Piclr PICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2PICLR22 Vcxo Interpolated Control Port Overview VIC Port Interface SignalsVIC Port Signal Direction Description Interface Operational Details Example Values for Interpolation Rate Enabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field Descriptions VIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Products Applications DSPRfid