Texas Instruments TMS320DM648 Video Port Peripheral Control Register PCR, Peren Soft Free, Stop

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GPIO Registers

5.1.2 Video Port Peripheral Control Register (PCR)

The video port peripheral control register (PCR) determines operation during emulation.

Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend. However, this will only work if one of the continuous capture/display modes is selected because non-continuous modes require CPU intervention for EDMAs to continue indefinitely (and the CPU is halted during emulation suspend).

When FREE = 0, emulation suspend can occur. Clocks and counters continue to run in order to maintain synchronization with external devices. The video port waits until a field boundary to halt EDMA event generation, so that upon restart the video port can begin generating events again at the precise point it left off. After exiting suspend, the video port waits for the correct field boundary to occur and then reenables EDMA events. The EDMA pointers will be at the correct location for capture/display to resume where it left off. The emulation suspend operation is similar to the BLKCAP or BLKDISP operation with the difference being that BLKCAP and BLKDISP operations take effect immediately rather than at field completion and rely on you to reset the EDMA mechanism before they are cleared.

There is no separate emulation suspend mechanism on the video capture side. The field and frame operation (see Table 3-6) can be used as emulation suspend.

The video port peripheral control register (PCR) is shown in Figure 5-2and described in Table 5-3.

Figure 5-2. Video Port Peripheral Control Register (PCR)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		PEREN	SOFT	FREE
R-0		R/W-0	R-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5-3. Video Port Peripheral Control Register (PCR) Field Descriptions

Bit	field (1)	symval (1)	Value	Description
31-3	Reserved		0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
2	PEREN	OF(value)		Peripheral enable bit.
		DEFAULT	0	Video port is disabled. Port clock (VCLK1, VCLK2, STCLK) inputs are gated off to
		DISABLE		save power. EDMA access to the video port is still acknowledged but indeterminate
				read data is returned and write data is discarded.
		ENABLE	1	Video port is enabled.
1	SOFT	OF(value)		Soft bit enable mode bit. This bit is used in conjunction with FREE bit to determine
				state of video port clock during emulation suspend. This bit has no effect if FREE = 1.
		DEFAULT	0	The current field is completed upon emulation suspend. After completion, no new
		STOP		EDMA events are generated. The port clocks and counters continue to run in order to
				maintain synchronization. No interrupts are generated. If the port is in display mode,
				video control signals continue to be output and the default data value is output during
				the active video window.
		COMP	1	Is not defined for this peripheral; the bit is hardwired to 0.
0	FREE	OF(value)		Free-running enable mode bit. This bit is used in conjunction with SOFT bit to
				determine state of video port during emulation suspend.
		SOFT	0	Free-running mode is disabled. During emulation suspend, SOFT bit determines
				operation of video port.
		DEFAULT	1	Free-running mode is enabled. Video port ignores the emulation suspend signal and
				continues to function as normal.

(1)For CSL implementation, use the notation VP_PCR_field_symval

SPRUEM1 –May 2007	General-Purpose I/O Operation	153
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