Texas Instruments TMS320DM648 manual Raw Mode RGB Output Support, Raw Data Fifo Unpacking

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Raw Data Display Mode

4.6.1 Raw Mode RGB Output Support

The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out. This option allows proper tracking of the display pixels when sending out sequential RGB samples. (INCPIX would be set to three in this case, to indicate that a single pixel is represented by three output samples.)

Sequential RGB samples output are also supported through a special FIFO unpacking mode. When the

8-bit raw 3/4 unpacking is selected (RGBX bit in VDCTL), three output bytes are selected from each word and the fourth byte is ignored. This allows the video port to correctly output data formatted as 24-bit RGB (or RGBα) words in memory.

4.6.2 Raw Data FIFO Unpacking

Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the display data pipeline. By default, data is unpacked from right to left .

The 8-bit raw mode uses a single data FIFO. Samples are unpacked as shown in Figure 4-21.

Figure 4-21. 8-Bit Raw FIFO Unpacking

VCLKOUT

VDOUT[9−2] Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9Raw 10 Raw 11

63

5655

4847

4039

3231

2423

1615

8 7

0

Raw 15

Raw 14

Raw 13

Raw 12

Raw 11

Raw 10

Raw 9

Raw 8

Raw FIFO

Raw 7

Raw 6

Raw 5

Raw 4

Raw 3

Raw 2

Raw 1

Raw 0

Little-EndianUnpacking

Figure 4-22shows the 16-bit raw mode. Samples are unpacked from each word of the FIFO.

Figure 4-22. 16-Bit Raw FIFO Unpacking

VCLKOUT

VDOUT[19−12]/VDOUT[9−2]		Raw 0 Raw 1	Raw 2 Raw 3 Raw 4 Raw 5		Raw 6 Raw 7 Raw 8 Raw	9 Raw 10 Raw 11
63		4847	3231		1615	0
	Raw 11		Raw 10		Raw 9		Raw 8
	Raw 7		Raw 6		Raw 5		Raw 4
	Raw 3		Raw 2		Raw 1		Raw 0
Raw FIFO				Little-EndianUnpacking

In 8-bit raw 3/4 mode, three samples are unpacked from the FIFO and the remaining byte is ignored. This is shown in Figure 4-23.

Figure 4-23. 8-Bit Raw

FIFO Unpacking

VCLKOUT

VDOUT[9−2]

Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11

(R0)

(G0)

(B0)

(R1)

(G1)

(B1)

(R2)

(G2)

(B2)

(R3)

(G3)

(B3)

63

5655

4847

4039

3231

2423

1615

8 7

0

Raw 11 (B3)

Raw 10 (G3)

Raw 9 (R3)

Raw 8 (B2)

Raw 7 (G2)

Raw 6 (R2)

Raw 5 (B1)

Raw 4 (G1)

Raw 3 (R1)

Raw 2 (B0)

Raw 1 (G0)

Raw 0 (R0)

Raw FIFO

Little-EndianUnpacking

SPRUEM1 –May 2007 Video Display Port 107

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