Texas Instruments TMS320DM648 Video Display Counter Reload Register Vdreload, Vrld, Crld Hrld

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					Video Display Registers
	Figure 4-50. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
31		28	27		16
	Reserved				VSYNCYSTOP2
	R-0				R/W-0
15		12	11		0
	Reserved				VSYNCXSTOP2
	R-0				R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Table 4-25. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Field
					Descriptions
Bit	field (1)	symval (1)		Value	Description
31-28	Reserved	-		0	Reserved. The reserved bit location is always read as 0. A value written to this
					field has no effect.
27-16	VSYNCYSTOP2	OF(value)		0-FFFh	Specifies the line where VSYNC is de-asserted for field 2.
		DEFAULT		0
15-12	Reserved	-		0	Reserved. The reserved bit location is always read as 0. A value written to this
					field has no effect.
11-0	VSYNCXSTOP2	OF(value)		0-FFFh	Specifies the pixel where VSYNC is de-asserted in field 2.
		DEFAULT		0

(1)For CSL implementation, use the notation VP_VDVSYNE2_field_symval

4.12.21 Video Display Counter Reload Register (VDRELOAD)

When external horizontal or vertical synchronization are used, the video display counter reload register (VDRELOAD) determines what values are loaded into the counters when an external sync is activated.

The video display counter reload register (VDRELOAD) is shown in Figure 4-51and described in Table 4-26.

Figure 4-51. Video Display Counter Reload Register (VDRELOAD)

31	28	27	16
	Reserved		VRLD
	R-0		R/W-0
15	12	11	0
	CRLD		HRLD
	R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 4-26. Video Display Counter Reload Register (VDRELOAD) Field Descriptions

Bit	field (1)	symval (1)	Value	Description
31-28	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
27-16	VRLD	OF(value)	0-FFFh	Value loaded into frame line counter (FLCOUNT) when external VSYNC occurs.
		DEFAULT	0
15-12	CRLD	OF(value)	0-Fh	Value loaded into video clock counter (VCCOUNT) when external HSYNC occurs.
		DEFAULT	0
11-0	HRLD	OF(value)	0-FFFh	Value loaded into frame pixel counter (FPCOUNT) when external HSYNC occurs.
		DEFAULT	0

(1)For CSL implementation, use the notation VP_VDRELOAD_field_symval

SPRUEM1 –May 2007	Video Display Port	141
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