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Texas Instruments TMS320DM648 manual Video Port Pin Data Set Register Pdset

Models: TMS320DM648

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GPIO Registers

5.1.7 Video Port Pin Data Set Register (PDSET)

PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s.

The video port pin data set register (PDSET) is shown in Figure 5-7and described in Table 5-8.

Figure 5-7. Video Port Pin Data Set Register (PDSET)

31							24
			Reserved
				R-0
23	22	21	20	19	18	17	16
Reserved	PDSET22	PDSET21	PDSET20	PDSET19	PDSET18	PDSET17	PDSET16
R-0	W-0	W-0	W-0	W-0	W-0	W-0	W-0
15	14	13	12	11	10	9	8
PDSET15	PDSET14	PDSET13	PDSET12	Reserved	Reserved	PDSET9	PDSET8
W-0	W-0	W-0	W-0	R-0	R-0	W-0	W-0
7	6	5	4	3	2	1	0
PDSET7	PDSET6	PDSET5	PDSET4	PDSET3	PDSET2	Reserved	Reserved
W-0	W-0	W-0	W-0	W-0	W-0	R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5-8. Video Port Pin Data Set Register (PDSET) Field Descriptions

Bit	field (1)	symval (1)	Value	Description
31-23	Reserved	-	0	Reserved. The reserved bit location is always read as 0. A value written to this field
				has no effect.
22	PDSET22	OF(value)		Allows PDOUT22 bit to be set to a logic high without affecting other I/O pins controlled
				by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL3HI	1	Sets PDOUT22 (VCTL3) bit to 1.
21	PDSET21	OF(value)		Allows PDOUT21 bit to be set to a logic high without affecting other I/O pins controlled
				by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL2HI	1	Sets PDOUT21 (VCTL2) bit to 1.
20	PDSET20	OF(value)		Allows PDOUT20 bit to be set to a logic high without affecting other I/O pins controlled
				by the same port.
		DEFAULT	0	No effect.
		NONE
		VCTL1HI	1	Sets PDOUT20 (VCTL1) bit to 1.
19-2	PDSET[19-2]	OF(value)		Allows PDOUT[19-2] bit to be set to a logic high without affecting other I/O pins
				controlled by the same port.
		DEFAULT	0	No effect.
		NONE
		VDATAnHI	1	Sets PDOUT[n] (VDATA[n]) bit to 1.

(1)For CSL implementation, use the notation VP_PDSET_PDSETn_symval

SPRUEM1 –May 2007	General-Purpose I/O Operation	161
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Texas Instruments TMS320DM648 manual Video Port Pin Data Set Register Pdset

Contents

Users Guide Submit Documentation Feedback Contents Raw Data Capture Mode BT.656 Image Display Video Display Registers Recommended Values Operational Details List of Figures Bit BT.656 Fifo Unpacking Video Display Event Register Vddispevt List of Tables Video Display Register Recommended Values Related Documentation From Texas Instruments About This ManualNotational Conventions Related Documentation From Texas Instruments Trademarks Overview Video Port Video Port Block Diagram Edma Interface Video Port FifoBT.656 Video Capture Fifo Configuration Video Capture Fifo ConfigurationsYsrca Y/C Video Capture Fifo Configuration Bit Raw Video Capture Fifo Configuration Video Display Fifo ConfigurationsBit Locked Raw Video Display Fifo Configuration Video Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Port Pin Mapping Video Capture Signal Mapping1Video Display Signal Mapping Vdin Data Bus Usage for Capture Modes1 Capture Mode BT.656 Raw Data Data Bus BitVdin Bus Usage for Capture Modes Video Port Pin Multiplexing Vdout Data Bus Usage for Display ModesVideoPort Clocking Vdout Data Bus Usage for Display Modes1Video Port Power-On Reset Reset OperationPeripheral Bus Reset Software Port ResetInterrupt Operation Capture Channel ResetDisplay Channel Reset Capture Edma Event Generation Edma OperationEdma Size and Threshold Restrictions Display Edma Event GenerationVideo Port Control Registers Edma Interface OperationVideo Port Control Registers Acronym Register NameDescription Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Operating Mode Video Port Operating Mode SelectionVideo Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Lfda DcnaLfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register VpisVideo Port Interrupt Status Register Vpis Field Descriptions Vdctl None ClearShort field detected on channel a interrupt detected bit Covra Video Capture Port BT.656 and Y/C Mode Field and Frame OperationBT.656 Video Capture Mode Video Capture Mode SelectionVideo Capture Mode Selection 1 BT.656 Capture ChannelsBT.656 Protection Bits Error Correction by Protection BitsVideo Capture Parameters 3 BT.656 Image Window and Capture5 BT.656 Fifo Packing 4 BT.656 Data SamplingCommon Video Source Parameters Video Source1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture4 Y/C Fifo Packing BT.656 and Y/C Mode Field and Frame OperationBit Y/C Fifo Packing VclkinaCapture Determination and Notification BT.656 and Y/C Mode Capture OperationVC xCTL Bit OperationVertical Synchronization Vertical Counter Reset PointVertical Synchronization Programming EAVVRST=0 VRST=1 FINV=0 FINV=1 Vcount Vcount Operation Example EXC =Horizontal Synchronization Horizontal Counter Reset PointHorizontal Synchronization Programming VCxCTL BitField Detect Method Field IdentificationField Identification Programming Video Input Filtering Short and Long Field DetectVclkin VSYNC# VCTL2 HSYNC# VCTL1Input Filter Modes 10. Input Filter Mode SelectionChrominance Re-sampling Operation Scaling Operation2 Scaled Co-Sited Filtering Edge Pixel Replication11. Edge Pixel Replication Ancillary Data CaptureHorizontal Ancillary Hanc Data Capture Raw Data Capture ModeVertical Ancillary Vanc Data Capture Raw Data Capture NotificationFrmc 11. Raw Data Mode Capture OperationRaw Data Fifo Packing TCI Data Capture TCI Capture ModeTCI Capture Features PCR TCI Capture Error DetectionSynchronizing the System Clock TCI Data Capture Notification 12. TCI Capture Mode OperationVcactl Bit Clear FrmcPerr Psterr Writing to the FifoReading from the Fifo Capture Line Boundary Conditions Capturing Video in BT.656 or Y/C ModeCapturing Video in Raw Data Mode Handling Fifo Overrun in BT.656 or Y/C ModeCapturing Data in TCI Capture Mode Handling Fifo Overrun Condition in Raw Data Mode13. Video Capture Control Registers Handling Fifo Overrun Condition in TCI Capture ModeVideo Capture Registers Vcfld Vcxpos Video Capture Channel x Status Register VCASTAT, VcbstatFsync Frmc F2C F1C Vcypos Description Bit BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel a Control Register Vcactl Rstch Blkcap None ResetRdfe Finv EXC Fldd Vrst Hrst Vcen Lfde Sfde ResmplEavfid FDL Eavsav ExternV1EAV V0EAVVideo Capture Channel x Field 1 Start Register VCxSTRT1 Value BT.656 or Y/C Mode Raw Data Mode TCI ModeVideo Capture Channel x Field 1 Stop Register VCxSTOP1 Vcxstop Video Capture Channel x Field 2 Start Register VCxSTRT2Vcystop 26. Video Capture Channel x Field 2 Stop Register VCxSTOP2 Video Capture Channel x Field 2 Stop Register VCxSTOP2Video Capture Channel x Vertical Interrupt Register VCxVINT VCTHRLD1 VCTHRLD2Video Capture Channel B Control Register Vcbctl Video Capture Channel x Event Count Register VCxEVTCTCAPEVTCT2 CAPEVTCT1Vrst Hrst Vcen 30. Video Capture Channel B Control Register VcbctlSAV or VCTL1 inactive edge Not used 24. TCI Capture Control Register Tcictl Field Descriptions BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI Capture Control Register Tcictl Inpcr TCI Clock Initialization LSB Register TciclkinitlTCI System Time Clock LSB Register Tcistclkl Bit Value ModeTCI Clock Initialization MSB Register Tciclkinitm TCI System Time Clock MSB Register Tcistclkm Default PcrmPcre Pcrm PcreATC TCI System Time Clock Compare LSB Register TcistcmplTCI System Time Clock Compare MSB Register Tcistcmpm TCI System Time Clock Compare Mask LSB Register Tcistmskl Value BT.656, Y/C Mode, or Raw Data Mode TCI ModeTCI System Time Clock Compare Mask MSB Register Tcistmskm AtcmTickct Value BT.656, Y/C Mode, or Raw Data Mode TCI M odeTCI System Time Clock Ticks Interrupt Register Tciticks Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw Data34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Registers Recommended Values Displaying Video in BT.656 or Y/C ModeVideo Display Field and Frame Operation Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingSmpte 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing BT.656 Video Display Mode Sync Signal GenerationExternal Sync Operation Port Sync OperationFpcount Vclkout Display Timing Reference CodesLine Number BT.656 Frame TimingLine Number 525/60 Description3 BT.656 Image Display Blanking Codes4 BT.656 Fifo Unpacking Vclkout1 Y/C Display Timing Reference Codes Y/C Video Display Mode2 Y/C Blanking Codes 3 Y/C Image Display4 Y/C Fifo Unpacking Output Filter Mode SelectionVideo Output Filtering Output Filter Modes2x Co-Sited Scaling 15. Chrominance Re-sampling18. Output Edge Pixel Replication 2x Interspersed ScalingAncillary Data Display Raw Data Display ModeHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output SupportDisplay Determination and Notification Video Display Field and Frame OperationDisplay Operation Vdctl BitDisplay Line Boundary Conditions Video Display Event GenerationInterlaced BT.656 Timing Example Display Timing ExamplesIpcount =IMGSIZE78 YfifoFrmwidth = IMGHOFF1 = Vclkin Fpcount Ipcount VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFlcount 112 26. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display ExampleVCTL1 Hsyncab Vclkout Vclkin FpcountIpcount VCTL1 Hblnkab 28. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example Hsyncstart = 1350 Hsyncstop = VCTL1 Hblnkac VCTL1 Hsyncac VclkoutFrmwidth = IMGHOFF1 = Hblnkstart = Flcount EAV Ilcount V F 30. Y/C Progressive Display Vertical Timing ExampleDisplaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Handling Under-run Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions Blanking Value BT.656 and Y/C Mode Raw Data ModeNone Frmdis None FlddisVideo Display Horizontal Blanking Register Vdhblnk Video Display Frame Size Register VdfrmszFrmheight FrmwidthField has no effect BT.656 and Y/C Mode Raw Data Mode 31-28 ReservedVBLNKXSTOP1 VBLNKYSTOP1VBLNKXSTART2 VBLNKYSTART2DEFAULT0 Value BT.656 and Y/C ModeVBLNKYSTOP2 VBLNKXSTOP2IMGVOFF1 Video Display Field 1 Image Offset Register VDIMGOFF1IMGHOFF1 None NegoffIMGHSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGVSIZE1 IMGHOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGVOFF2 Video Display Field 1 Timing Register VDFLDT1 Video Display Field 2 Image Size Register VDIMGSZ2IMGVSIZE2 IMGHSIZE2FLD1YSTART Video Display Field 2 Timing Register VDFLDT2FLD1XSTART FLD2YSTARTVDTHRLD2 Video Display Threshold Register VdthrldIncpix VDTHRLD1Hsyncstart Video Display Horizontal Synchronization Register VdhsyncHsyncstop VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2Vrld Video Display Counter Reload Register VdreloadCrld Hrld CrldVideo Display Clipping Register Vdclip Video Display Event Register VddispevtDISPEVT2 DISPEVT1Clipchigh Video Display Default Display Value Register VddefvalCrdefval Cbdefval Video Display Vertical Interrupt Register VdvintDefval Crdefval56. Video Display Vertical Interrupt Register Vdvint Video Display Field Bit Register VdfbitFbitclr FbitsetVBITCLR1 VBITSET1VBITSET2 VBITCLR2Register Field 525/60 Value Video Display Registers Recommended Values34. Video Display Register Recommended Values Video Display Fifo Registers Display Mode35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGeneral-Purpose I/O Operation Offset Address Acronym Register Name Gpio RegistersVideo Port Registers Type Video Port Peripheral Identification Register VppidClass Revision ClassPeren Soft Free Video Port Peripheral Control Register PCRPeren StopVideo Port Pin Function Register Pfunc Field Descriptions Video Port Pin Function Register PfuncNormal VDATA0TO9 Normal VDATA10TO19Video Port Pin Direction Register Pdir Field Descriptions Video Port Pin Direction Register PdirVDATA8TO9IN VDATA8TO9OUT VDATA12TO15IN VDATA12TO15OUTVDATA4TO7IN VDATA4TO7OUT VDATA0T32IN VDATA0T32OUTVideo Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Input Register PdinVideo Port Pin Data Out Register Pdout Field Descriptions Video Port Pin Data Output Register PdoutPDOUT9 PDOUT8 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 PDOUT22When writing data, writes to PDOUT20 bit Video Port Pin Data Set Register Pdset Field Descriptions Video Port Pin Data Set Register PdsetVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Data Clear Register PdclrPIEN22 Video Port Pin Interrupt Enable Register PienPIEN9 PIEN8 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 Value Description Video Port Pin Interrupt Polarity Register PipolPISTAT22 Video Port Pin Interrupt Status Register PistatNone VCTL3INT None VCTL2INTPICLR22 Video Port Pin Interrupt Clear Register PiclrPICLR9 PICLR8 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 Vcxo Interpolated Control Port VIC Port Signal Direction Description VIC Port Interface SignalsOverview InterfaceExample Values for Interpolation Rate Operational DetailsVIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlVicinbits VIC Input Register VicinVIC Input Register Vicin Field Descriptions Vicclkdiv VIC Clock Divider Register VicdivVIC Clock Divider Register Vicdiv Field Descriptions Rfid Products ApplicationsDSP