Texas Instruments TMS320DM648 manual Video Port Pin Mapping, Video Capture Signal Mapping1

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Video Port Pin Mapping

1.4Video Port Pin Mapping

The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1-1. Pin functionality detail for video display mode is listed in Table 1-2. All unused port signals (except VCLK1 and VCLK1) can be configured as general-purpose I/O (GPIO) pins.

Table 1-1. Video Capture Signal Mapping(1)

				Usage
		BT.656 Capture Mode			Raw Data Capture Mode
			Single	Y/C Capture			TCI Capture
Video Port Signal	I/O	Dual Channel	Channel	Mode	8-Bit	16-Bit	Mode
VDATA[9-2]	I/O	VDIN[9-2]	VDIN[9-2]	VDIN[9-2]	VDIN[9-2]	VDIN[9-2]	VDIN[9-2]
		(In) Ch A	(In) Ch A	(In) (Y)	(In) Ch A	(In)	(In)
VDATA[19-12]	I/O	VDIN[19-12]	Not Used	VDIN[19-12]	VDIN[19-12]	VDIN[19-12]	Not Used
		(In) Ch B		(In) (Cb/Cr)	(In) Ch B	(In)
VCLK1	I	VCLKINA (In)	VCLKINA (In)	VCLKINA (In)	VCLKINA (In)	VCLKINA (In)	VCLKINA (In)
VCLK1	I/O	VCLKINB (In)	Not Used	Not Used	VCLKINB (In)	Not Used	Not Used
VCTL1	I/O	CAPENA	CAPENA/	CAPENA/	CAPENA	CAPENA	CAPENA
		(In)	AVID/HSYNC	AVID/HSYNC	(In)	(In)	(In)
			(In)	(In)
VCTL2	I/O	CAPENB	VBLNK/	VBLNK/	CAPENB	Not Used	PACSTRT
		(In)	VSYNC (In)	VSYNC (In)	(In)		(In)
VCTL3	I/O	Not Used	FID	FID	FID (In)	FID (In)	PACERR
			(In)	(In)	Ch A	Ch A	(In)

(1)Legend: VCLKINA – Channel A capture clock; CAPENA – Channel A capture enable; VCLKINB – Channel B capture clock; CAPENB – Channel B capture enable; AVID – Active video; HSYNC – Horizontal synchronization; VBLNK – Vertical blanking; VSYNC – Vertical synchronization; FID – Field identification; PACSTRT – Packet start; PACERR – Packet error

Table 1-2. Video Display Signal Mapping

				Usage
		BT.656 Display	Y/C Display	Raw Data Display Mode
Video Port Signal	I/O	Mode	Mode	8-Bit	16-Bit	8-Bit Dual Sync
VDATA[9-2]	I/O	VDOUT[9-2]	VDOUT[9-2]	VDOUT[9-2]	VDOUT[9-2]	VDOUT[9-2]
		(Out)	(Out) (Y)	(Out)	(Out)	(Out) (Ch A)
VDATA[19-12]	I/O	Not Used	VDOUT[19-12]	Not Used	VDOUT[19-12]	VDOUT[19-12]
			(Out) (Cb/Cr)		(Out)	(Out) (Ch B)
VCLK1	I	VCLKIN (In)	VCLKIN (In)	VCLKIN (In)	VCLKIN (In)	VCLKIN (In)
VCLK1	I/O	VCLKOUT (Out)	VCLKOUT (Out)	VCLKOUT (Out)	VCLKOUT (Out)	VCLKOUT (Out)
VCTL1	I/O	HSYNC/HBLNK/	HSYNC/HBLNK/	HSYNC/HBLNK/	HSYNC/HBLNK/	HSYNC/HBLNK/
		AVID/FLD (Out)	AVID/FLD (Out)	AVID/FLD (Out)	AVID/FLD (Out)	AVID/FLD (Out)
		or HSYNC (In)	or HSYNC (In)	or HSYNC (In)	or HSYNC (In)	or HSYNC (In)
VCTL2	I/O	VSYNC/VBLNK/C	VSYNC/VBLNK/C	VSYNC/VBLNK/C	VSYNC/VBLNK/C	VSYNC/VBLNK/C
		SYNC/FLD (Out)	SYNC/FLD (Out)	SYNC/FLD (Out)	SYNC/FLD (Out)	SYNC/FLD (Out)
		or VSYNC (In)	or VSYNC (In)	or VSYNC (In)	or VSYNC (In)	or VSYNC (In)
VCTL3	I/O	CBLNK/FLD	CBLNK/FLD	CBLNK/FLD	CBLNK/FLD	CBLNK/FLD
		(Out) or FLD (In)	(Out) or FLD (In)	(Out) or FLD (In)	(Out) or FLD (In)	(Out) or FLD (In)

26 Overview SPRUEM1 –May 2007

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