Texas Instruments TMS320C64x DSP manual

Contents

Main Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Trademarks Contents Page Page Page Page Page Figures Page Page Page Tables Page Page Overview Chapter 1 1.1 Video Port Page Figure 11. Video Port Block Diagram 1.2 Video Port FIFO 1.2.1 DMA Interface 1.2.2 Video Capture FIFO Configurations Figure 12. BT.656 Video Capture FIFO Configuration Figure 13. 8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration Figure 14. Y/C Video Capture FIFO Configuration Figure 15. 16/20-Bit Raw Video Capture FIFO Configuration 1.2.3 Video Display FIFO Configurations Figure 16. BT.656 Video Display FIFO Configuration Figure 17. 8/10-Bit Raw Video Display FIFO Configuration Figure 18. 8/10 Bit Locked Raw Video Display FIFO Configuration Figure 19. 16/20-Bit Raw Video Display FIFO Configuration Figure 110. Y/C Video Display FIFO Configuration 1.3 Video Port Registers Video Port Pin Mapping 1-13OverviewSPRU629 1.4 Video Port Pin Mapping Mode 8/10-Bit 16/20-Bit TSI Capture Table 11. Video Capture Signal Mapping Usage BT.656 Capture Mode Raw Data Capture Mode Video Port Signal I/O Dual Channel Single Channel Y/C Capture Table 12. Video Display Signal Mapping Display Mode Y/C Display Usage Video Port Signal I/O BT.656 Mode 8/10-Bit 16/20-Bit 8/10-Bit Dual Sync 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 13. Table 13. VDIN Data Bus Usage for Capture Modes 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 14. Table 14. VDOUT Data Bus Usage for Display Modes Video Port Chapter 2 2.1 Reset Operation 2.1.1 Power-On Reset 2.1.2 Peripheral Bus Reset 2.1.3 Software Port Reset 2.1.4 Capture Channel Reset 2.1.5 Display Channel Reset 2.2 Interrupt Operation 2.3 DMA Operation 2.3.1 Capture DMA Event Generation Figure 21. Capture DMA Event Generation Flow Diagram 2.3.2 Display DMA Event Generation DMA Operation 2-9Video PortSPRU629 Figure 22. Display DMA Event Generation Flow Diagram 2.3.3 DMA Size and Threshold Restrictions 2.3.4 DMA Interface Operation 2.4 Clocks Table 21. Video Port Functional Clocks 2.5 Video Port Functionality Subsets 2.5.1 Data Bus Width 2.5.2 FIFO Size 2.6 Video Port Throughput and Latency 2.6.1 Video Capture Throughput Table 22. Y/C Video Capture FIFO Capacity 2.6.2 Video Display Throughput Table 23. Raw Video Display FIFO Capacity 2.7 Video Port Control Registers Table 24. Video Port Control Registers 2.7.1 Video Port Control Register (VPCTL) Figure 23. Video Port Control Register (VPCTL) Table 25. Video Port Control Register (VPCTL) Field Descriptions Page Table 25. Video Port Control Register (VPCTL) Field Descriptions (Continued) Table 26. Video Port Operating Mode Selection 2.7.2 Video Port Status Register (VPSTAT) Figure 24. Video Port Status Register (VPSTAT) Table 27. Video Port Status Register (VPSTAT) Field Descriptions 2.7.3 Video Port Interrupt Enable Register (VPIE) Figure 25. Video Port Interrupt Enable Register (VPIE) Table 28. Video Port Interrupt Enable Register (VPIE) Field Descriptions Page Table 28. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued) 2.7.4 Video Port Interrupt Status Register (VPIS) Figure 26. Video Port Interrupt Status Register (VPIS) Table 29. Video Port Interrupt Status Register (VPIS) Field Descriptions Page Page Page Page Page Video Capture Port Chapter 3 3.1 Video Capture Mode Selection Table 31. Video Capture Mode Selection 3.2 BT.656 Video Capture Mode 3.2.1 BT.656 Capture Channels 3.2.2 BT.656 Timing Reference Codes Table 32. BT.656 Video Timing Reference Codes Table 33. BT.656 Protection Bits Table 34. Error Correction by Protection Bits Table 34. Error Correction by Protection Bits (Continued) 3.2.3 BT.656 Image Window and Capture Figure 31. Video Capture Parameters Table 35. Common Video Source Parameters 3.2.4 BT.656 Data Sampling 3-9Video Capture PortSPRU629 3.2.5 BT.656 FIFO Packing Figure 32. 8-Bit BT.656 FIFO Packing VCLKINA / VCLKINB VDIN[92] / VDIN[912] Video Capture Port3-10 SPRU629 Figure 33. 10-Bit BT.656 FIFO Packing 3-11Video Capture PortSPRU629 Figure 34. 10-Bit BT.656 Dense FIFO Packing 3.3 Y/C Video Capture Mode 3.3.1 Y/C Capture Channels 3.3.2 Y/C Timing Reference Codes 3.3.3 Y/C Image Window and Capture Video Capture Port3-14 SPRU629 3.3.4 Y/C FIFO Packing Figure 35. 8-Bit Y/C FIFO Packing 3-15Video Capture PortSPRU629 Figure 36. 10-Bit Y/C FIFO Packing Video Capture Port3-16 SPRU629 Figure 37. 10-Bit Y/C Dense FIFO Packing 3.4 BT.656 and Y/C Mode Field and Frame Operation 3.4.1 Capture Determination and Notification Table 36. BT.656 and Y/C Mode Capture Operation Table 36. BT.656 and Y/C Mode Capture Operation (Continued) 3.4.2 Vertical Synchronization Table 37. Vertical Synchronization Programming BT.656 and Y/C Mode Field and Frame Operation 3-21Video Capture PortSPRU629 Figure 38. VCOUNT Operation Example (EXC = 0) Field 2 Active Field 2 Blanking Line VF 3.4.3 Horizontal Synchronization Table 38. Horizontal Synchronization Programming BT.656 and Y/C Mode Field and Frame Operation 3-23Video Capture PortSPRU629 Figure 39. HCOUNT Operation Example (EXC = 0) Figure 310. HCOUNT Operation Example (EXC = 1) 3.4.4 Field Identification Table 39. Field Identification Programming Figure 311.Field 1 Detection Timing 3.4.5 Short and Long Field Detect 3.5 Video Input Filtering 3.5.1 Input Filter Modes Table 310. Input Filter Mode Selection 3.5.2 Chrominance Resampling Operation Figure 312. Chrominance Resampling 3.5.3 Scaling Operation Figure 313. 1/2 Scaled Co-Sited Filtering Figure 314. 1/2 Scaled Chrominance Resampled Filtering 3.5.4 Edge Pixel Replication Figure 315. Edge Pixel Replication Figure 316. Capture Window Not Requiring Edge Pixel Replication 3.6 Ancillary Data Capture 3.6.1 Horizontal Ancillary (HANC) Data Capture 3.6.2 Vertical Ancillary (VANC) Data Capture 3.7 Raw Data Capture Mode 3.7.1 Raw Data Capture Notification Table 311. Raw Data Mode Capture Operation 3.7.2 Raw Data FIFO Packing Video Capture Port3-34 SPRU629 Figure 317. 8-Bit Raw Data FIFO Packing Figure 318. 10-Bit Raw Data FIFO Packing 3-35Video Capture PortSPRU629 Figure 319. 10-Bit Dense Raw Data FIFO Packing Figure 320. 16-Bit Raw Data FIFO Packing Video Capture Port3-36 SPRU629 Figure 321. 20-Bit Raw Data FIFO Packing 3.8 TSI Capture Mode 3.8.1 TSI Capture Features 3.8.2 TSI Data Capture Figure 322. Parallel TSI Capture 3.8.3 TSI Capture Error Detection 3.8.4 Synchronizing the System Clock Figure 323. Program Clock Reference (PCR) Header Format Figure 324. System Time Clock Counter Operation 3.8.5 TSI Data Capture Notification Table 312. TSI Capture Mode Operation 3.8.6 Writing to the FIFO Figure 325. TSI FIFO Packing Figure 326. TSI Timestamp Format (Little Endian) Figure 327. TSI Timestamp Format (Big Endian) 3.8.7 Reading from the FIFO 3.9 Capture Line Boundary Conditions Figure 328. Capture Line Boundary Example 3.10 Capturing Video in BT.656 or Y/C Mode 3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode 3.11 Capturing Video in Raw Data Mode 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode 3.12 Capturing Data in TSI Capture Mode 3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode 3.13 Video Capture Registers Table 313. Video Capture Control Registers Table 313. Video Capture Control Registers (Continued) 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) Figure 329. Video Capture Channel x Status Register (VCASTAT, VCBSTAT) Table 314. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Table 314. Video Capture Channel x Status Register (VCxSTAT) 3.13.2 Video Capture Channel A Control Register (VCACTL) Figure 330. Video Capture Channel A Control Register (VCACTL) Field Descriptions Page Page Page Page 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) Figure 331. Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) Table 316. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions 3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) Figure 332. Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) Table 317. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Descriptions 3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) Figure 333. Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) Table 318. Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions 3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) Figure 334. Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) Table 319. Video Capture Channel x Field 2 Stop Register (VCxSTOP2) Field Descriptions 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) Figure 335. Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) Table 320. Video Capture Channel x Vertical Interrupt Register (VCxVINT) 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) Figure 336. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) Table 321. Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions 3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) Figure 337. Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) Table 322. Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions 3.13.10 Video Capture Channel B Control Register (VCBCTL) Figure 338. Video Capture Channel B Control Register (VCBCTL) Field Descriptions Page Page Page 3.13.11 TSI Capture Control Register (TSICTL) Figure 339. TSI Capture Control Register (TSICTL) Table 324. TSI Capture Control Register (TSICTL) Field Descriptions 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) Figure 340. TSI Clock Initialization LSB Register (TSICLKINITL) Table 325. TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) Figure 341. TSI Clock Initialization MSB Register (TSICLKINITM) Table 326. TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) Figure 342. TSI System Time Clock LSB Register (TSISTCLKL) Table 327. TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) Figure 343. TSI System Time Clock MSB Register (TSISTCLKM) Table 328. TSI System Time Clock MSB Register (TSISTCLKM) Field Descriptions 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) Figure 344. TSI System Time Clock Compare LSB Register (TSISTCMPL) Table 329. TSI System Time Clock Compare LSB Register (TSISTCMPL) 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) Figure 345. TSI System Time Clock Compare MSB Register (TSISTCMPM) Table 330. TSI System Time Clock Compare MSB Register (TSISTCMPM) 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) Figure 346. TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) Table 331. TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) Figure 347. TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) Table 332. TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) Figure 348. TSI System Time Clock Ticks Interrupt Register (TSITICKS) Table 333.TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Descriptions 3.14 Video Capture FIFO Registers Table 334. Video Capture FIFO Registers Table 335. Video Capture FIFO Registers Function Video Display Port Chapter 4 4.1 Video Display Mode Selection Table 41. Video Display Mode Selection 4.1.1 Image Timing Figure 41. NTSC Compatible Interlaced Display Figure 42. SMPTE 296M Compatible Progressive Scan Display Figure 43. Interlaced Blanking Intervals and Video Areas Figure 44. Progressive Blanking Intervals and Video Area 4.1.2 Video Display Counters Figure 45. Horizontal Blanking and Horizontal Sync Timing Figure 46. Vertical Blanking, Sync and Even/Odd Frame Signal Timing 4.1.3 Sync Signal Generation 4.1.4 External Sync Operation 4.1.5 Port Sync Operation Figure 47. Video Display Module Synchronization Chain 4.2 BT.656 Video Display Mode Figure 48. BT.656 Output Sequence 4.2.1 Display Timing Reference Codes Figure 49. 525/60 BT.656 Horizontal Blanking Timing Video Display Port4-10 SPRU629 Figure 410. 625/50 BT.656 Horizontal Blanking Timing Active VideoBlanking One Line Next Line Table 42. BT.656 Frame Timing Figure 411.Digital Vertical F and V Transitions 4.2.2 Blanking Codes 4.2.3 BT.656 Image Display 4-13Video Display PortSPRU629 4.2.4 BT.656 FIFO Unpacking Figure 412. 8-Bit BT.656 FIFO Unpacking Video Display Port4-14 SPRU629 For 10-bit BT.656 operation, two samples are unpacked from each word as shown in Figure 413. Figure 413. 10-Bit BT.656 FIFO Unpacking 4-15Video Display PortSPRU629 Figure 414. BT.656 Dense FIFO Unpacking Video Display Port4-16 SPRU629 4.3 Y/C Video Display Mode VDOUT[1910] 4 Active VideoBlanking 4.3.1 Y/C Display Timing Reference Codes 4.3.2 Y/C Blanking Codes 4.3.3 Y/C Image Display 4.3.4 Y/C FIFO Unpacking Video Display Port4-18 SPRU629 VDOUT[1912] Cb 4 Cb 5Cr 4 Cr 5 Figure 416. 8-Bit Y/C FIFO Unpacking 4-19Video Display PortSPRU629 For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 417. VDOUT[1910] Cb 0 Cb 1 Cb 2 Cb 3Cr 0 Cr 1 Cr 2 Cr 3 Cb 4 Cb 5Cr 4 Cr 5 Figure 417. 10-Bit Y/C FIFO Unpacking Video Display Port4-20 SPRU629 VDOUT[1910] Cb 0 Cb 1 Cb 2 Cb 3Cr 0 Cr 1 Cr 2 Cr 3 Cb 4 Cb 5Cr 4 Cr 5 Figure 418. 10-Bit Y/C Dense FIFO Unpacking 4.4 Video Output Filtering 4.4.1 Output Filter Modes Table 43. Output Filter Mode Selection 4.4.2 Chrominance Resampling Operation Figure 419. Chrominance Resampling 4.4.3 Scaling Operation Video Output Filtering 4-23Video Display PortSPRU629 Figure 420. 2x Co-Sited Scaling Figure 421. 2x Interspersed Scaling 4.4.4 Edge Pixel Replication Figure 422. Output Edge Pixel Replication Video Output Filtering Figure 423. Luma Edge Replication Figure 424. Interspersed Chroma Edge Replication 4.5 Ancillary Data Display 4.5.1 Horizontal Ancillary (HANC) Data Display 4.5.2 Vertical Ancillary (VANC) Data Display 4.6 Raw Data Display Mode 4.6.1 Raw Mode RGB Output Support 4.6.2 Raw Data FIFO Unpacking Figure 425. 8-Bit Raw FIFO Unpacking 4-27Video Display PortSPRU629 For 10-bit operation, two samples are unpacked from each FIFO word. This is shown in Figure 426. Figure 426. 10-Bit Raw FIFO Unpacking Figure 427. 10-Bit Raw Dense FIFO Unpacking Video Display Port4-28 SPRU629 Figure 428 shows the 16-bit raw mode. Two samples are unpacked from each word of the FIFO. Figure 428. 16-Bit Raw FIFO Unpacking Figure 429. 20-Bit Raw FIFO Unpacking 4-29Video Display PortSPRU629 Figure 430. 8-Bit Raw 3/4 FIFO Unpacking Figure 431. 10-Bit Raw 3/4 FIFO Unpacking 4.7 Video Display Field and Frame Operation 4.7.1 Display Determination and Notification Table 44. Display Operation Table 44. Display Operation (Continued) 4.7.2 Video Display Event Generation 4.8 Display Line Boundary Conditions Display Line Boundary Conditions Video Display Port4-34 SPRU629 Figure 432. Display Line Boundary Example Cr FIFO VDOUT[1912] Cb 40 Cb 41Cr 40 Cr 41 IPCOUNT = IMGSIZE(78) 4.9 Display Timing Examples 4.9.1 Interlaced BT.656 Timing Example 4-36 Video Display Port SPRU629 Figure 433. BT.656 Interlaced Display Horizontal Timing Example Page Video Display Port4-38 SPRU629 Figure 434. BT.656 Interlaced Display Vertical Timing Example FLCOUNT ILCOUNT VF EAV 4.9.2 Interlaced Raw Display Example 4-40 Video Display Port SPRU629 Figure 435. Raw Interlaced Display Horizontal Timing Example Page Video Display Port4-42 SPRU629 Figure 436. Raw Interlaced Display Vertical Timing Example 4.9.3 Y/C Progressive Display Example 4-44 Video Display Port SPRU629 Figure 437. Y/C Progressive Display Horizontal Timing Example Blanking Active Video EAV Blanking Data SAV EAV VCLKIN IPCOUNT VCTL1 (HBLNK) VCTL1 (HSYNC) Page Video Display Port4-46 SPRU629 Figure 438. Y/C Progressive Display Vertical Timing Example 4.10 Displaying Video in BT.656 or Y/C Mode Page 4.11 Displaying Video in Raw Data Mode Page 4.11.1 Handling Underrun Condition of the Display FIFO 4.12 Video Display Registers Table 45. Video Display Control Registers Table 45. Video Display Control Registers (Continued) 4.12.1 Video Display Status Register (VDSTAT) Figure 439. Video Display Status Register (VDSTAT) Table 46. Video Display Status Register (VDSTAT) Field Descriptions 4.12.2 Video Display Control Register (VDCTL) Figure 440. Video Display Control Register (VDCTL) Table 47. Video Display Control Register (VDCTL) Field Descriptions Page Page Page Page 4.12.3 Video Display Frame Size Register (VDFRMSZ) Figure 441. Video Display Frame Size Register (VDFRMSZ) Table 48. Video Display Frame Size Register (VDFRMSZ) Field Descriptions 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) Figure 442. Video Display Horizontal Blanking Register (VDHBLNK) Table 49. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Figure 443. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Table 410. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Figure 444. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Table 411. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Figure 445. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Table 412. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Figure 446. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Table 413. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) Figure 447. Video Display Field 1 Image Offset Register (VDIMGOFF1) Table 414. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) Figure 448. Video Display Field 1 Image Size Register (VDIMGSZ1) Table 415. Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) Figure 449. Video Display Field 2 Image Offset Register (VDIMGOFF2) Table 416. Video Display Field 2 Image Offset Register (VDIMGOFF2) 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) Figure 450. Video Display Field 2 Image Size Register (VDIMGSZ2) Table 417. Video Display Field 2 Image Size Register (VDIMGSZ2) Field Descriptions 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) Figure 451. Video Display Field 1 Timing Register (VDFLDT1) Table 418. Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) Figure 452. Video Display Field 2 Timing Register (VDFLDT2) Table 419. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions 4.12.15 Video Display Threshold Register (VDTHRLD) Figure 453. Video Display Threshold Register (VDTHRLD) Table 420. Video Display Threshold Register (VDTHRLD) Field Descriptions 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) Figure 454. Video Display Horizontal Synchronization Register (VDHSYNC) Table 421. Video Display Horizontal Synchronization Register (VDHSYNC) 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Figure 455. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Table 422. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Figure 456. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Table 423. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) Figure 457. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) Table 424. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Figure 458. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Table 425. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) 4.12.21 Video Display Counter Reload Register (VDRELOAD) Figure 459. Video Display Counter Reload Register (VDRELOAD) Table 426. Video Display Counter Reload Register (VDRELOAD) Field Descriptions 4.12.22 Video Display Display Event Register (VDDISPEVT) Figure 460. Video Display Display Event Register (VDDISPEVT) Table 427. Video Display Display Event Register (VDDISPEVT) Field Descriptions 4.12.23 Video Display Clipping Register (VDCLIP) Figure 461. Video Display Clipping Register (VDCLIP) Table 428. Video Display Clipping Register (VDCLIP) Field Descriptions 4.12.24 Video Display Default Display Value Register (VDDEFVAL) Figure 462. Video Display Default Display Value Register (VDDEFVAL) Figure 463. Video Display Default Display Value Register (VDDEFVAL)Raw Data Mode Table 429. Video Display Default Display Value Register (VDDEFVAL) Field Descriptions 4.12.25 Video Display Vertical Interrupt Register (VDVINT) Figure 464. Video Display Vertical Interrupt Register (VDVINT) Table 430. Video Display Vertical Interrupt Register (VDVINT) Field Descriptions 4.12.26 Video Display Field Bit Register (VDFBIT) Figure 465. Video Display Field Bit Register (VDFBIT) Table 431. Video Display Field Bit Register (VDFBIT) Field Descriptions 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Figure 466. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Table 432. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Figure 467. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Table 433. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) 4.13 Video Display Registers Recommended Values Table 434. Video Display Register Recommended Values Table 434. Video Display Register Recommended Values (Continued) 4.14 Video Display FIFO Registers Table 435. Video Display FIFO Registers Table 436. Video Display FIFO Registers Function Page 5.1 GPIO Registers Table 51. Video Port Registers 5.1.1 Video Port Peripheral Identification Register (VPPID) Figure 51. Video Port Peripheral Identification Register (VPPID) Table 52. Video Port Peripheral Identification Register (VPPID) Field Descriptions 5.1.2 Video Port Peripheral Control Register (PCR) Figure 52. Video Port Peripheral Control Register (PCR) Table 53. Video Port Peripheral Control Register (PCR) Field Descriptions 5.1.3 Video Port Pin Function Register (PFUNC) Figure 53. Video Port Pin Function Register (PFUNC) Table 54. Video Port Pin Function Register (PFUNC) Field Descriptions Table 54. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued) 5.1.4 Video Port Pin Direction Register (PDIR) Figure 54. Video Port Pin Direction Register (PDIR) Table 55. Video Port Pin Direction Register (PDIR) Field Descriptions Page Table 55. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued) 5.1.5 Video Port Pin Data Input Register (PDIN) Figure 55. Video Port Pin Data Input Register (PDIN) Table 56. Video Port Pin Data Input Register (PDIN) Field Descriptions 5.1.6 Video Port Pin Data Output Register (PDOUT) Figure 56. Video Port Pin Data Output Register (PDOUT) Table 57. Video Port Pin Data Out Register (PDOUT) Field Descriptions 5.1.7 Video Port Pin Data Set Register (PDSET) Figure 57. Video Port Pin Data Set Register (PDSET) Table 58. Video Port Pin Data Set Register (PDSET) Field Descriptions 5.1.8 Video Port Pin Data Clear Register (PDCLR) Figure 58. Video Port Pin Data Clear Register (PDCLR) Table 59. Video Port Pin Data Clear Register (PDCLR) Field Descriptions 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) Figure 59. Video Port Pin Interrupt Enable Register (PIEN) Table 510. Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) Figure 510. Video Port Pin Interrupt Polarity Register (PIPOL) Table 511. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) Figure 511.Video Port Pin Interrupt Status Register (PISTAT) Table 512. Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) Figure 512. Video Port Pin Interrupt Clear Register (PICLR) Table 513. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions VCXO Interpolated Control Port Chapter 6 This chapter provides an overview of the VCXO interpolated control (VIC) port. 6.1 Overview Figure 61. TSI System Block Diagram 6.2 Interface Table 61. VIC Port Interface Signals 6.3 Operational Details Figure 62. Program Clock Reference (PCR) Header Format Equation 61. Relationship Between Interpolation Rate and Input Frequency 6.4 Enabling VIC Port 6.5 VIC Port Registers Table 63. VIC Port Registers 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 63 and described in Table 64. Figure 63. VIC Control Register (VICCTL) Table 64. VIC Control Register (VICCTL) Field Descriptions Table 64. VIC Control Register (VICCTL) Field Descriptions (Continued) 6.5.2 VIC Input Register (VICIN) Figure 64. VIC Input Register (VICIN) Table 65. VIC Input Register (VICIN) Field Descriptions 6.5.3 VIC Clock Divider Register (VICDIV) Figure 65. VIC Clock Divider Register (VICDIV) Table 66. VIC Clock Divider Register (VICDIV) Field Descriptions Video Port Configuration Examples A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format Page Page Page Page Page Page Page A.2 Example 2: Noncontinuous Frame Display for 525/60 Format Page Page Page Page Page Page Page Page Page Page Index A B C D E F G H I L M N O P R Page S T V Page Page Y