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Texas Instruments TMS320C64x DSP manual VBITCLR1, VBITSET1

Models: TMS320C64x DSP

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Video Display Registers

4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)

The video display field 1 vertical blanking bit register (VDVBIT1) controls the V bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1 is shown in Figure 4–66 and described in Table 4–32.

The VBITSET1 and VBITCLR1 bits control the V bit value in the EAV and SAV timing control codes. The V bit is set to 1 (indicating the start of field 1 digital vertical blanking) in the EAV code at the beginning of the line whenever the frame line counter (FLCOUNT) is equal to VBITSET1. It remains a 1 for all EAV/SAV codes until the EAV at the beginning of the line on when FLCOUNT = VBITCLR1 where it changes to 0 (indicating the start of the field 1 digital active display). The V bit operation is completely independent of the VBLNK control signal.

The VBITSET1 and VBITCLR1 bits should be programmed so that FLCOUNT becomes set to 1 during field 1 vertical blanking. The hardware only starts generating field 1 EDMA events when FLCOUNT = 1.

Figure 4–66. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)

31	28	27	16
	Reserved		VBITCLR1

	R-0		R/W-0
15	12	11	0

	Reserved		VBITSET1

	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

4-90

Video Display Port

SPRU629

Image 235

Texas Instruments TMS320C64x DSP manual VBITCLR1, VBITSET1

Contents

Literature Number SPRU629 April Important Notice Read This First Trademarks Contents Video Capture Port Discusses operation of the video capture portVCASTOP2, VCBSTOP2 VCASTRT1, VCBSTRT1VCASTOP1, VCBSTOP1 VCASTRT2, VCBSTRT211.1 General Purpose I/O Operation VDVSYNE2Vcxo Interpolated Control Port Figures Xii Figures Xiii Video Port Tables Xvi Tables Xvii Topic OverviewVideo Port SPRU629 Channel B VCLK1 VCLK2 VCTL1 VCTL2VCTL3 Channel aDMA Interface Video Port FifoYsrca Cbsrca Crsrca Ysrcb Cbsrcb Crsrcb Video Capture Fifo ConfigurationsYsrca Ysrca Cbsrca Crsrca Y/C Video Capture Fifo ConfigurationYdsta Cbdst Crdst Video Display Fifo Configurations10-Bit Raw Video Display Fifo Configuration Ydstb YdstaVideo Port Registers 10. Y/C Video Display Fifo ConfigurationVideo Port Pin Mapping Video Capture Signal MappingUsage Raw Data Display Mode Video Display Signal MappingVdin Data Bus Usage for Capture Modes Capture Mode BT.656 Raw DataData Bus 10-Bit 16-Bit 20-Bit Mode Vdin Bus Usage for Capture ModesVdout Data Bus Usage for Display Modes Vdout Data Bus Usage for Display ModesVideo Port Power-On Reset Reset OperationPeripheral Bus Reset Capture Channel Reset Software Port ResetDisplay Channel Reset Interrupt Operation Capture DMA Event Generation DMA OperationFifo ≥ Capture DMA Event Generation Flow DiagramDisplay DMA Event Generation Display DMA Event Generation Flow Diagram DMA Size and Threshold Restrictions DMA Interface Operation Data Bus Width ClocksVideo Port Functionality Subsets Video Port Functional ClocksFifo Size Video Port Throughput and LatencyVideo Capture Throughput Bit Bit Dense 10-Bit Y/C Video Capture Fifo CapacityRaw Video Display Fifo Capacity Video Display ThroughputBit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280 Video Port Control Registers Video Port Control RegistersAcronym Register Name Section Value Description Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions BitNone Activelow None ClearVCLK2P None ReverseOperating Mode Video Port Operating Mode SelectionVpctl Bit Video Port Status Register Vpstat Field Descriptions Video Port Status Register VpstatVideo Port Interrupt Enable Register Vpie Ccmpb SerrbDcna Lfda Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra Video Port Interrupt Status Register VpisDcna Dcmp Tick STCVcount = Ystop Vcbctl Out of the port. The DMA complete interrupt can be used to BT.656 or Y/C capture mode Lfda is set when long field Vcactl Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionTSI Bit Cmode Bits Mode Description 1 BT.656 Capture Channels BT.656 Video Capture ModeBT.656 Video Timing Reference Codes 2 BT.656 Timing Reference CodesReceived F, V, and H Bits Error Correction by Protection BitsBT.656 Protection Bits Line Information Bits Protection Bits010 011 100 101 3 BT.656 Image Window and CaptureP 0 Bits Common Video Source Parameters Video Capture Parameters4 BT.656 Data Sampling Bit BT.656 Fifo Packing 5 BT.656 Fifo PackingVDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y Bit BT.656 Dense Fifo Packing 1 Y/C Capture Channels Y/C Video Capture Mode2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture Bit Y/C Fifo Packing 4 Y/C Fifo PackingVDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing Bit Y/C Dense Fifo Packing Capture Determination and Notification BT.656 and Y/C Mode Field and Frame OperationVC xCTL Bit BT.656 and Y/C Mode Capture OperationOperation VCxCTL Bit Vertical SynchronizationVertical Synchronization Programming Vertical Counter Reset PointVC xCTL Bit VMode Vcount Operation Example EXC = VCxCTL Bit HMode Horizontal Counter Reset PointHorizontal Synchronization Horizontal Synchronization ProgrammingHcount Operation Example EXC = EAV code Field IdentificationField Identification Programming Field Detect MethodShort and Long Field Detect 11.Field 1 Detection TimingFilter Operation 10. Input Filter Mode SelectionVideo Input Filtering Input Filter ModesScaling Operation Chrominance Resampling Operation13 /2 Scaled Co-Sited Filtering SAV Edge Pixel ReplicationEAV Xstart Xsize SAV 16. Capture Window Not Requiring Edge Pixel ReplicationHorizontal Ancillary Hanc Data Capture Ancillary Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture Notification Raw Data Capture ModeRaw Data Fifo Packing 11. Raw Data Mode Capture Operation17 -Bit Raw Data Fifo Packing 19 -Bit Dense Raw Data Fifo Packing 21 -Bit Raw Data Fifo Packing TSI Capture Features TSI Capture ModeTSI Data Capture Synchronizing the System Clock TSI Capture Error DetectionVclkin Capen Pacstrt Ctmode PCRTSI Data Capture Notification 12. TSI Capture Mode OperationVcactl Bit Perr Writing to the FifoVclkin TSI TSI FifoReading from the Fifo Capture Line Boundary ConditionsFifo Ipcount = IMGHSIZE78 VclkoutCapturing Video in BT.656 or Y/C Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Handling Fifo Overrun Condition in Raw Data Mode Capturing Data in TSI Capture ModeHandling Fifo Overrun Condition in TSI Capture Mode 13. Video Capture Control Registers Video Capture RegistersVideo Capture Channel x Status Register VCASTAT, Vcbstat Description Bit BT.656 or Y/C Mode Raw Data Mode TSI ModeVcfld Value BT.656 or Y/C Mode Raw Data Mode TSI ModeDetected Video Capture Channel a Control Register Vcactl FIELD2 BlockRdfe FIELD1V0EAV EavfidFDL V1EAVCON ‡ HalfDescription Raw Data Mode TSI Mode SSE VcystartVCXSTART/VCVBLNKP Vcvblnkp VcxstartVcxstop VcystopField† Symval† FFFh Last captured line Not used VINT1 VIF2 FSCL2VINT2 VIF1VIF2 SPRU629 VCTHRLD1 VCTHRLD2CAPEVTCT1 CAPEVTCT2Vrst Hrst Vcen PK10B Lfde Sfde Resmpl Video Capture Channel B Control Register VcbctlCON Frame CF2 CF1 F1C, F2C, and Frmc status bits, in VCBSTAT, are not EAV or Not used VCTL1 active edge Capture field Not used CON‡Enstc Tcken Sten Ctmode TSI Capture Control Register Tsictl24. TSI Capture Control Register Tsictl Field Descriptions Value BT.656, Y/C Mode TSI Mode Or Raw Data ModeBit Field BT.656, Y/C Mode TSI Mode Or Raw Data ModeTSI Clock Initialization LSB Register Tsiclkinitl InpcrInpcrm TSI Clock Initialization MSB Register TsiclkinitmInpcre 42. TSI System Time Clock LSB Register Tsistclkl TSI System Time Clock LSB Register TsistclklPcre Pcrm TSI System Time Clock MSB Register TsistclkmPcre ATC TSI System Time Clock Compare LSB Register Tsistcmpl45. TSI System Time Clock Compare MSB Register Tsistcmpm TSI System Time Clock Compare MSB Register TsistcmpmAtcm TSI System Time Clock Compare Mask LSB Register TsistmsklTSI System Time Clock Compare Mask MSB Register Tsistmskm Tickct TSI System Time Clock Ticks Interrupt Register Tsiticks35. Video Capture Fifo Registers Function Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 34. Video Capture Fifo RegistersVideo Display Port Image Timing Video Display Mode SelectionVideo Display Mode Selection Dmode Bits Mode DescriptionNtsc Compatible Interlaced Display Interlaced Blanking Intervals and Video Areas Video Display Counters Progressive Blanking Intervals and Video AreaFpcount Horizontal Blanking and Horizontal Sync TimingVsync Sync Signal GenerationFlcount VblnkPort Sync Operation External Sync OperationDisplay Timing Reference Codes BT.656 Video Display ModeLine Number BT.656 Frame Timing11.Digital Vertical F and V Transitions 3 BT.656 Image Display Blanking Codes12 -Bit BT.656 Fifo Unpacking 4 BT.656 Fifo Unpacking13 -Bit BT.656 Fifo Unpacking 14. BT.656 Dense Fifo Unpacking 1 Y/C Display Timing Reference Codes Y/C Video Display Mode3 Y/C Image Display 2 Y/C Blanking Codes4 Y/C Fifo Unpacking 16 -Bit Y/C Fifo Unpacking 17 -Bit Y/C Fifo Unpacking 18 -Bit Y/C Dense Fifo Unpacking Vdctl Bit Output Filter Mode SelectionVideo Output Filtering Output Filter Modes19. Chrominance Resampling 20 x Co-Sited Scaling 23. Luma Edge Replication Vertical Ancillary Vanc Data Display Raw Data Display ModeAncillary Data Display Horizontal Ancillary Hanc Data DisplayRaw Data Fifo Unpacking Raw Mode RGB Output Support26 -Bit Raw Fifo Unpacking 28 -Bit Raw Fifo Unpacking 30 -Bit Raw 3/4 Fifo Unpacking Display Determination and Notification Video Display Field and Frame OperationCON Frame DF2 DF1 Display OperationVideo Display Event Generation Display Line Boundary Conditions 32. Display Line Boundary Example Interlaced BT.656 Timing Example Display Timing Examples33. BT.656 Interlaced Display Horizontal Timing Example SPRU629 34. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example 35. Raw Interlaced Display Horizontal Timing SPRU629 36. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example 37. Y/C Progressive Display Horizontal Timing Example SPRU629 38. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode Handling Underrun Condition of the Display Fifo Video Display Control Registers Video Display RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Field Descriptions Output Disable EnableBlkdis FXSValue BT.656 and Y/C Mode Raw Data Mode Blanking RgbxFlddis FrmdisFrmheight Video Display Frame Size Register VdfrmszFrmwidth Hbdla Video Display Horizontal Blanking Register VdhblnkHblnkstop DelayHblnkstart VBLNKXSTART1 VBLNKYSTART1VBLNKXSTOP1 VBLNKYSTOP1Field† Symval† VBLNKXSTART2 VBLNKYSTART2VBLNKXSTOP2 VBLNKYSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGHOFF1 IMGVOFF1Negoff IMGVSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGHSIZE1 IMGVOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGHOFF2 None IMGVSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2IMGHSIZE2 FLD1YSTART Video Display Field 1 Timing Register VDFLDT1FLD1XSTART FLD2YSTART Video Display Field 2 Timing Register VDFLDT2FLD2XSTART Incpix Video Display Threshold Register VdthrldVDTHRLD1 VDTHRLD2Hsyncstop Video Display Horizontal Synchronization Register VdhsyncHsyncstart VSYNCXSTART1 VSYNCYSTART1VSYNCXSTOP1 VSYNCYSTOP1VSYNCXSTART2 VSYNCYSTART2VSYNCXSTOP2 VSYNCYSTOP2Crld Video Display Counter Reload Register VdreloadVrld HrldDISPEVT2 Video Display Display Event Register VddispevtDISPEVT1 Clipclow Video Display Clipping Register VdclipClipchigh Clipyhigh ClipylowCrdefval Cbdefval Video Display Default Display Value Register VddefvalYdefval Crdefval Defval64. Video Display Vertical Interrupt Register Vdvint Video Display Vertical Interrupt Register VdvintFbitset Video Display Field Bit Register VdfbitFbitclr VBITSET1 VBITCLR1Field† Symval† VBITSET2 VBITCLR2Field† Symval† 34. Video Display Register Recommended Values Video Display Registers Recommended ValuesRegister Field 525/60 Value 625/50 Value VDVBIT1 VBITSET1 VDVSYNS2 VSYNCXSTART2VDVSYNE2 VSYNCXSTOP2 Vdfbit Fbitclr FbitsetRegister BT.656 or Y/C Raw Data Video Display Fifo Registers35. Video Display Fifo Registers 36. Video Display Fifo Registers FunctionGpio Registers General Purpose I/O OperationVideo Port Registers Gpio RegistersClass Video Port Peripheral Identification Register VppidType Class RevisionSoft Free Video Port Peripheral Control Register PCRComp PerenSoft StopNormal Video Port Pin Function Register PfuncVideo Port Pin Function Register Pfunc Field Descriptions PFUNC22PFUNC0 PFUNC20PFUNC10 VDATA10TO19VCTL3IN Video Port Pin Direction Register PdirVideo Port Pin Direction Register Pdir Field Descriptions PDIR22PDIR20 PDIR21VCTL2IN VCTL2OUTPDIR4 PDIR8VDATA8TO9IN VDATA8TO9OUTPDIN7 PDIN6 Video Port Pin Data Input Register PdinPDIN20 PDIN12Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Output Register Pdout PDOUT21 Video Port Pin Data Out Register Pdout Field DescriptionsPDOUT20 Video Port Pin Data Set Register Pdset PDSET21 Video Port Pin Data Set Register Pdset Field DescriptionsPDSET20 Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register PdclrVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien Video Port Pin Interrupt Enable Register PienPIEN20 PIEN21PIPOL13 PIPOL12 Video Port Pin Interrupt Polarity Register PipolPIPOL21 PIPOL20 PIPOL19 PIPOL17 PIPOL16 PIPOL15PIPOL21 PIPOL22VCTL3ACTHI VCTL3ACTLOVideo Port Pin Interrupt Status Register Pistat PISTAT20 PISTAT22VCTL3INT VCTL2INTPICLR4 Video Port Pin Interrupt Clear Register PiclrPICLR21 PICLR22PICLR20 Vcxo Interpolated Control Port Overview Operational Details VIC Port Interface SignalsVIC Port Signal Direction Description InterfaceExample Values for Interpolation Rate VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl Field Descriptions VIC Control Register VicctlGO bit can be written to at any time VIC Input Register Vicin Field Descriptions VIC Input Register VicinVicinbits VIC Clock Divider Register Vicdiv Field Descriptions VIC Clock Divider Register VicdivVicclkdiv Video Port Configuration Examples VCAIMGHSIZE2 * VCAIMGVSIZE2 Example 1 Noncontinuous Frame Capture for 525/60 FormatFrame VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1 VPVCASTRT1SSEENABLE, VCAXSTART1 Vpvcactlblkcapclear SPRU629 Vcayedmafrmcnt Edmaoptrmk Edmaoptprimedium Vdhblnkstop Vdhblnkstart + Example 2 Noncontinuous Frame Display for 525/60 FormatDefine vertical blanking bitVDVBITn reg values VDIMGHSIZE1 * VDIMGVSIZE1 Dmode VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2 Vpvdstatfrmdclear Vdyedmafrmcnt Vdyedmaelecnt Example 2 Noncontinuous Frame Display for 525/60 Format EDMAOPT2DSYES Index Index-2 Index-3 Pin data set register Pdset Pin direction register Pdir Vcaevtct Vdhblnk Index-7 Vddefval Vddispevt Index-9 Ydsta Ydstb