Figures

3–21 20-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-363–22 Parallel TSI Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-383–23 Program Clock Reference (PCR) Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-393–24 System Time Clock Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-393–25 TSI FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413–26 TSI Timestamp Format (Little Endian) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413–27 TSI Timestamp Format (Big Endian) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-423–28 Capture Line Boundary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-433–29 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) . . . . . . . . . . . . . . . . . . . 3-503–30 Video Capture Channel A Control Register (VCACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-533–31 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) . . . . . . . . . . 3-583–32 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) . . . . . . . . . . 3-603–33 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) . . . . . . . . . . 3-613–34 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) . . . . . . . . . . 3-623–35 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) . . . . . . . . . . 3-633–36 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) . . . . . . . . . . . . 3-663–37 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) . . . . . . . . . . 3-673–38 Video Capture Channel B Control Register (VCBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-683–39 TSI Capture Control Register (TSICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-723–40 TSI Clock Initialization LSB Register (TSICLKINITL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-743–41 TSI Clock Initialization MSB Register (TSICLKINITM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-753–42 TSI System Time Clock LSB Register (TSISTCLKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-763–43 TSI System Time Clock MSB Register (TSISTCLKM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-773–44 TSI System Time Clock Compare LSB Register (TSISTCMPL) . . . . . . . . . . . . . . . . . . . . . 3-783–45 TSI System Time Clock Compare MSB Register (TSISTCMPM) . . . . . . . . . . . . . . . . . . . . 3-793–46 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) . . . . . . . . . . . . . . . 3-803–47 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) . . . . . . . . . . . . . . 3-813–48 TSI System Time Clock Ticks Interrupt Register (TSITICKS) . . . . . . . . . . . . . . . . . . . . . . . 3-82

4–1 NTSC Compatible Interlaced Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4–2 SMPTE 296M Compatible Progressive Scan Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4–3 Interlaced Blanking Intervals and Video Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4–4 Progressive Blanking Intervals and Video Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4–5 Horizontal Blanking and Horizontal Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4–6 Vertical Blanking, Sync and Even/Odd Frame Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4–7 Video Display Module Synchronization Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4–8 BT.656 Output Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4–9 525/60 BT.656 Horizontal Blanking Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94–10 625/50 BT.656 Horizontal Blanking Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104–11 Digital Vertical F and V Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114–12 8-Bit BT.656 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134–13 10-Bit BT.656 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144–14 BT.656 Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154–15 Y/C Horizontal Blanking Timing (BT.1120 60I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164–16 8-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

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Texas Instruments TMS320C64x DSP manual Xii
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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