Displaying Video in BT.656 or Y/C Mode

12)Configure a DMA to move data from the Y buffer in the DSP memory to YDSTA (memory-mapped Y display FIFO). The transfers should be triggered by the YEVT.

13)Configure a DMA to move data from the Cb buffer in the DSP memory to CBDST (memory-mapped Cb display FIFO). The transfers should be triggered by the CbEVT. The size of the transfers should be set to ½ the Y transfer size.

14)Configure a DMA to move data from the Cr buffer in the DSP memory to CRDST (memory-mapped Cr display FIFO). The transfers should be triggered by the CrEVT. The size of the transfers should be set to ½ the Y transfer size.

15)Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total doublewords per field divided by total doublewords per Y DMA.

16)Write to VPIE to enable underrun (DUND) and display complete (DCMP) interrupts, if desired.

17)Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits).

18)Write to VDCTL to:

-Set display mode (DMODE = 00x for BT.656 output, 10x for Y/C output).

-Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).

-Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external sync inputs (HXS, VXS, FXS bits).

-Enable scaling (SCALE and RESMPL bits), if desired and in 8-bit mode.

-Select 10-bit unpacking mode (DPK bit), if appropriate.

-Set VDEN bit to enable the display.

19)Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized.

20)Write to VDCTL to clear the BLKDIS bit.

21)Display is enabled at the start of the first frame after BLKDIS = 0 and begins with the first selected field. DMA events are generated as triggered by VDTHRLD and the DEVTCT counter. When a selected field has been displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH), the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is enabled in VPIE.

4-48

Video Display Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Displaying Video in BT.656 or Y/C Mode
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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