Texas Instruments TMS320C64x DSP BT.656 Protection Bits, Error Correction by Protection Bits

BT.656 Video Capture Mode

Bits P0, P1, P2, and P3 have different states depending on the state of bits F, V, and H as shown in Table 3–3.

Table 3–3. BT.656 Protection Bits

	Line Information Bits				Protection Bits
F	V	H		P3	P2	P1	P0
0	0	0	0		0	0	0
0	0	1	1		1	0	1
0	1	0	1		0	1	1
0	1	1	0		1	1	0
1	0	0	0		1	1	1
1	0	1	1		0	1	0
1	1	0	1		1	0	0
1	1	1	0		0	0	1

The protection bits allow the port to implement a DEDSEC (double error detec- tion, single error correction) function on the received video timing reference code. The corrected values for the F, H, and V bits based on the protection bit values are shown in Table 3–4. The – entries indicate detected double bit errors that cannot be corrected. Detection of these errors causes the SERRx bit in the video port interrupt status register (VPIS) to be set.

Table 3–4. Error Correction by Protection Bits

Received F, V, and H Bits

Received
	000	001	010	011	100	101	110	111
P3–P0Bits
0000	000	000	000	–	000	–	–	111
0001	000	–	–	111	–	111	111	111
0010	000	–	–	011	–	101	–	–
0011	–	–	010	–	100	–	–	111
0100	000	–	–	011	–	–	110	–
0101	–	001	–	–	100	–	–	111
0110	–	011	011	011	100	–	–	011

SPRU629 Video Capture Port 3-5