Figures

4–17 10-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194–18 10-Bit Y/C Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-204–19 Chrominance Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-224–20 2x Co-Sited Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-234–21 2x Interspersed Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-234–22 Output Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-234–23 Luma Edge Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-244–24 Interspersed Chroma Edge Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-244–25 8-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-264–26 10-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-274–27 10-Bit Raw Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-274–28 16-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-284–29 20-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-284–30 8-Bit Raw 3/4 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-294–31 10-Bit Raw 3/4 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-294–32 Display Line Boundary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-344–33 BT.656 Interlaced Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-364–34 BT.656 Interlaced Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-384–35 Raw Interlaced Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-404–36 Raw Interlaced Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-424–37 Y/C Progressive Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-444–38 Y/C Progressive Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-464–39 Video Display Status Register (VDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-534–40 Video Display Control Register (VDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-554–41 Video Display Frame Size Register (VDFRMSZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-604–42 Video Display Horizontal Blanking Register (VDHBLNK) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-614–43 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) . . . . . . . . . . . . . . . . . 4-634–44 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . . . . . . . . . . 4-644–45 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . . . . . . . . . . . 4-664–46 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . . . . . . . . . . 4-674–47 Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . . . . . . . . . . 4-694–48 Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-704–49 Video Display Field 2 Image Offset Register (VDIMGOFF2) . . . . . . . . . . . . . . . . . . . . . . . 4-714–50 Video Display Field 2 Image Size Register (VDIMGSZ2) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-734–51 Video Display Field 1 Timing Register (VDFLDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-744–52 Video Display Field 2 Timing Register (VDFLDT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-754–53 Video Display Threshold Register (VDTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-764–54 Video Display Horizontal Synchronization Register (VDHSYNC) . . . . . . . . . . . . . . . . . . . . 4-784–55 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) . . . . . . . . . . 4-794–56 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) . . . . . . . . . . 4-804–57 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) . . . . . . . . . . 4-814–58 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) . . . . . . . . . . 4-824–59 Video Display Counter Reload Register (VDRELOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-834–60 Video Display Display Event Register (VDDISPEVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84

SPRU629

Figures

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Texas Instruments TMS320C64x DSP manual Figures Xiii
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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