Texas Instruments TMS320C64x DSP manual Vcystop, Vcxstop

Video Capture Registers

3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1)

The video capture channel x field 1 stop register (VCASTOP1, VCBSTOP1) defines the end of the field 1-captured image or the end of the raw data or TSI packet. VCxSTOP1 is shown in Figure 3–32 and described in Table 3–17.

In raw capture mode, the horizontal and vertical counters are combined into a single counter that keeps track of the total number of samples received.

In TSI capture mode, the horizontal and vertical counters are combined into a single data counter that keeps track of the total number of bytes received. The capture starts when a SYNC byte is detected. The data counter counts bytes as they are received. The FRMC bit (in VCxSTAT) gets set each time a packet has been received.

Figure 3–32. Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1)

31	28	27	16
	Reserved		VCYSTOP
	R-0		R/W-0
15	12	11	0
	Reserved		VCXSTOP
	R-0		R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 3–17. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Descriptions

					Description
Bit	field†	symval†	Value	BT.656 or Y/C Mode	Raw Data Mode	TSI Mode
31–28	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A
				value written to this field has no effect.
27–16	VCYSTOP	OF(value)	0–FFFh	Last captured line.	Upper 12 bits of the	Upper 12 bits of
					data size (in data	the data size (in
					samples).	data samples).
15–12	Reserved	–	0	Reserved. The reserved bit location is always read as 0. A
				value written to this field has no effect.
11–0	VCXSTOP	OF(value)	0–FFFh	Last captured pixel	Lower 12 bits of the	Lower 12 bits of
				(VCXSTOP – 1).	data size (in data	the data size (in
				Must be an even	samples).	data samples).
				value (the LSB is
				treated as 0).

† For CSL implementation, use the notation VP_VCxSTOP1_field_symval

3-60 Video Capture Port SPRU629