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Texas Instruments TMS320C64x DSP manual SPRU629

Models: TMS320C64x DSP

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Display Timing Examples

The vertical output timing for raw mode is shown in Figure 4–36. This example outputs the same 480-line window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case. The active field 1 is 242.5-lines high and active field 2 is 242.5-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFF1 of 2 lines and an IMGVOFF2 of 3 lines and also results in a nondata half-line at the end of field 1 and at the beginning of field 2 due to their noninteger line lengths.

The VBLNK and VSYNC signals are shown as they would be output for active- low operation. Note that only one of the two signals is actually available exter- nally. The VBLNK and VSYNC edges for field 1 occur at the end of an active line so their XSTART/XSTOP values are set to 720 (start of blanking). For field 2, VBLNK and VSYNC edges occur during the middle of the active horizontal line so their XSTART/XSTOP values are set to 360.

The FLD output is setup to transition at the start of each analog field (start of vertical blanking). There is no EAV[F] bit in raw mode, so FLD1YSTRT is set to 1, FLD2YSTART is set to 263, FBITCLR and FBITSET are ignored. Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line.

The active horizontal output column shows the output data during the active portion of the horizontal line. Note that in raw mode there is no blanking data value so the default value is output for the active portion of all nonimage window lines.

SPRU629

Video Display Port

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Texas Instruments TMS320C64x DSP manual SPRU629

Contents

Literature Number SPRU629 April Important Notice Read This First Trademarks Contents Discusses operation of the video capture port Video Capture PortVCASTRT2, VCBSTRT2 VCASTRT1, VCBSTRT1VCASTOP1, VCBSTOP1 VCASTOP2, VCBSTOP211.1 VDVSYNE2 General Purpose I/O OperationVcxo Interpolated Control Port Figures Xii Figures Xiii Video Port Tables Xvi Tables Xvii Overview TopicVideo Port SPRU629 Channel a VCLK1 VCLK2 VCTL1 VCTL2VCTL3 Channel BVideo Port Fifo DMA InterfaceVideo Capture Fifo Configurations Ysrca Cbsrca Crsrca Ysrcb Cbsrcb CrsrcbYsrca Y/C Video Capture Fifo Configuration Ysrca Cbsrca CrsrcaVideo Display Fifo Configurations Ydsta Cbdst Crdst10-Bit Raw Video Display Fifo Configuration Ydsta Ydstb10. Y/C Video Display Fifo Configuration Video Port RegistersVideo Capture Signal Mapping Video Port Pin MappingVideo Display Signal Mapping Usage Raw Data Display ModeVdin Bus Usage for Capture Modes Capture Mode BT.656 Raw DataData Bus 10-Bit 16-Bit 20-Bit Mode Vdin Data Bus Usage for Capture ModesVdout Data Bus Usage for Display Modes Vdout Data Bus Usage for Display ModesVideo Port Reset Operation Power-On ResetPeripheral Bus Reset Software Port Reset Capture Channel ResetDisplay Channel Reset Interrupt Operation DMA Operation Capture DMA Event GenerationCapture DMA Event Generation Flow Diagram Fifo ≥Display DMA Event Generation Display DMA Event Generation Flow Diagram DMA Size and Threshold Restrictions DMA Interface Operation Video Port Functional Clocks ClocksVideo Port Functionality Subsets Data Bus WidthVideo Port Throughput and Latency Fifo SizeVideo Capture Throughput Y/C Video Capture Fifo Capacity Bit Bit Dense 10-BitVideo Display Throughput Raw Video Display Fifo CapacityBit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280 Video Port Control Registers Video Port Control RegistersAcronym Register Name Section Bit Video Port Control Register VpctlVideo Port Control Register Vpctl Field Descriptions Value DescriptionNone Reverse None ClearVCLK2P None ActivelowVideo Port Operating Mode Selection Operating ModeVpctl Bit Video Port Status Register Vpstat Video Port Status Register Vpstat Field DescriptionsVideo Port Interrupt Enable Register Vpie Serrb CcmpbDcna Lfda Tick STC Video Port Interrupt Status Register VpisDcna Dcmp Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVcount = Ystop Vcbctl Out of the port. The DMA complete interrupt can be used to BT.656 or Y/C capture mode Lfda is set when long field Vcactl Video Capture Port Video Capture Mode Selection Video Capture Mode SelectionTSI Bit Cmode Bits Mode Description BT.656 Video Capture Mode 1 BT.656 Capture Channels2 BT.656 Timing Reference Codes BT.656 Video Timing Reference CodesLine Information Bits Protection Bits Error Correction by Protection BitsBT.656 Protection Bits Received F, V, and H Bits3 BT.656 Image Window and Capture 010 011 100 101P 0 Bits Video Capture Parameters Common Video Source Parameters4 BT.656 Data Sampling 5 BT.656 Fifo Packing Bit BT.656 Fifo PackingVDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y Bit BT.656 Dense Fifo Packing Y/C Video Capture Mode 1 Y/C Capture Channels2 Y/C Timing Reference Codes 3 Y/C Image Window and Capture 4 Y/C Fifo Packing Bit Y/C Fifo PackingVDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing Bit Y/C Dense Fifo Packing BT.656 and Y/C Mode Field and Frame Operation Capture Determination and NotificationBT.656 and Y/C Mode Capture Operation VC xCTL BitOperation Vertical Synchronization VCxCTL BitVertical Counter Reset Point Vertical Synchronization ProgrammingVC xCTL Bit VMode Vcount Operation Example EXC = Horizontal Synchronization Programming Horizontal Counter Reset PointHorizontal Synchronization VCxCTL Bit HModeHcount Operation Example EXC = Field Detect Method Field IdentificationField Identification Programming EAV code11.Field 1 Detection Timing Short and Long Field DetectInput Filter Modes 10. Input Filter Mode SelectionVideo Input Filtering Filter OperationChrominance Resampling Operation Scaling Operation13 /2 Scaled Co-Sited Filtering Edge Pixel Replication SAVEAV 16. Capture Window Not Requiring Edge Pixel Replication Xstart Xsize SAVAncillary Data Capture Horizontal Ancillary Hanc Data CaptureVertical Ancillary Vanc Data Capture Raw Data Capture Mode Raw Data Capture Notification11. Raw Data Mode Capture Operation Raw Data Fifo Packing17 -Bit Raw Data Fifo Packing 19 -Bit Dense Raw Data Fifo Packing 21 -Bit Raw Data Fifo Packing TSI Capture Mode TSI Capture FeaturesTSI Data Capture TSI Capture Error Detection Synchronizing the System ClockVclkin Capen Pacstrt PCR Ctmode12. TSI Capture Mode Operation TSI Data Capture NotificationVcactl Bit TSI TSI Fifo Writing to the FifoVclkin PerrCapture Line Boundary Conditions Reading from the FifoIpcount = IMGHSIZE78 Vclkout FifoCapturing Video in BT.656 or Y/C Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Capturing Data in TSI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeHandling Fifo Overrun Condition in TSI Capture Mode Video Capture Registers 13. Video Capture Control RegistersVideo Capture Channel x Status Register VCASTAT, Vcbstat BT.656 or Y/C Mode Raw Data Mode TSI Mode Description BitValue BT.656 or Y/C Mode Raw Data Mode TSI Mode VcfldDetected Video Capture Channel a Control Register Vcactl FIELD1 BlockRdfe FIELD2V1EAV EavfidFDL V0EAVHalf CON ‡Description Raw Data Mode TSI Mode Vcystart SSEVCXSTART/VCVBLNKP Vcxstart VcvblnkpVcystop VcxstopField† Symval† FFFh Last captured line Not used VIF1 VIF2 FSCL2VINT2 VINT1VIF2 SPRU629 VCTHRLD2 VCTHRLD1CAPEVTCT2 CAPEVTCT1Video Capture Channel B Control Register Vcbctl Vrst Hrst Vcen PK10B Lfde Sfde ResmplCON Frame CF2 CF1 F1C, F2C, and Frmc status bits, in VCBSTAT, are not EAV or Not used VCTL1 active edge CON‡ Capture field Not usedTSI Capture Control Register Tsictl Enstc Tcken Sten CtmodeValue BT.656, Y/C Mode TSI Mode Or Raw Data Mode 24. TSI Capture Control Register Tsictl Field DescriptionsInpcr BT.656, Y/C Mode TSI Mode Or Raw Data ModeTSI Clock Initialization LSB Register Tsiclkinitl Bit FieldTSI Clock Initialization MSB Register Tsiclkinitm InpcrmInpcre TSI System Time Clock LSB Register Tsistclkl 42. TSI System Time Clock LSB Register TsistclklTSI System Time Clock MSB Register Tsistclkm Pcre PcrmPcre TSI System Time Clock Compare LSB Register Tsistcmpl ATCTSI System Time Clock Compare MSB Register Tsistcmpm 45. TSI System Time Clock Compare MSB Register TsistcmpmTSI System Time Clock Compare Mask LSB Register Tsistmskl AtcmTSI System Time Clock Compare Mask MSB Register Tsistmskm TSI System Time Clock Ticks Interrupt Register Tsiticks Tickct34. Video Capture Fifo Registers Capture Mode Register BT.656 or Y/C Raw DataVideo Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Port Dmode Bits Mode Description Video Display Mode SelectionVideo Display Mode Selection Image TimingNtsc Compatible Interlaced Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing FpcountVblnk Sync Signal GenerationFlcount VsyncExternal Sync Operation Port Sync OperationBT.656 Video Display Mode Display Timing Reference CodesBT.656 Frame Timing Line Number11.Digital Vertical F and V Transitions Blanking Codes 3 BT.656 Image Display4 BT.656 Fifo Unpacking 12 -Bit BT.656 Fifo Unpacking13 -Bit BT.656 Fifo Unpacking 14. BT.656 Dense Fifo Unpacking Y/C Video Display Mode 1 Y/C Display Timing Reference Codes2 Y/C Blanking Codes 3 Y/C Image Display4 Y/C Fifo Unpacking 16 -Bit Y/C Fifo Unpacking 17 -Bit Y/C Fifo Unpacking 18 -Bit Y/C Dense Fifo Unpacking Output Filter Modes Output Filter Mode SelectionVideo Output Filtering Vdctl Bit19. Chrominance Resampling 20 x Co-Sited Scaling 23. Luma Edge Replication Horizontal Ancillary Hanc Data Display Raw Data Display ModeAncillary Data Display Vertical Ancillary Vanc Data DisplayRaw Mode RGB Output Support Raw Data Fifo Unpacking26 -Bit Raw Fifo Unpacking 28 -Bit Raw Fifo Unpacking 30 -Bit Raw 3/4 Fifo Unpacking Video Display Field and Frame Operation Display Determination and NotificationDisplay Operation CON Frame DF2 DF1Video Display Event Generation Display Line Boundary Conditions 32. Display Line Boundary Example Display Timing Examples Interlaced BT.656 Timing Example33. BT.656 Interlaced Display Horizontal Timing Example SPRU629 34. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example 35. Raw Interlaced Display Horizontal Timing SPRU629 36. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example 37. Y/C Progressive Display Horizontal Timing Example SPRU629 38. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode Handling Underrun Condition of the Display Fifo Video Display Registers Video Display Control RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions BT.656 and Y/C Mode Raw Data Mode Video Display Control Register VdctlVideo Display Control Register Vdctl Field Descriptions FXS Disable EnableBlkdis OutputValue BT.656 and Y/C Mode Raw Data Mode Rgbx BlankingFrmdis FlddisVideo Display Frame Size Register Vdfrmsz FrmheightFrmwidth Video Display Horizontal Blanking Register Vdhblnk HbdlaDelay HblnkstopHblnkstart VBLNKYSTART1 VBLNKXSTART1VBLNKYSTOP1 VBLNKXSTOP1Field† Symval† VBLNKYSTART2 VBLNKXSTART2VBLNKYSTOP2 VBLNKXSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 IMGVOFF1 IMGHOFF1Negoff Video Display Field 1 Image Size Register VDIMGSZ1 IMGVSIZE1IMGHSIZE1 Video Display Field 2 Image Offset Register VDIMGOFF2 IMGVOFF2IMGHOFF2 None Video Display Field 2 Image Size Register VDIMGSZ2 IMGVSIZE2IMGHSIZE2 Video Display Field 1 Timing Register VDFLDT1 FLD1YSTARTFLD1XSTART Video Display Field 2 Timing Register VDFLDT2 FLD2YSTARTFLD2XSTART Video Display Threshold Register Vdthrld IncpixVDTHRLD2 VDTHRLD1Video Display Horizontal Synchronization Register Vdhsync HsyncstopHsyncstart VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2VSYNCYSTOP2 VSYNCXSTOP2Hrld Video Display Counter Reload Register VdreloadVrld CrldVideo Display Display Event Register Vddispevt DISPEVT2DISPEVT1 Clipyhigh Clipylow Video Display Clipping Register VdclipClipchigh ClipclowVideo Display Default Display Value Register Vddefval Crdefval CbdefvalYdefval Defval CrdefvalVideo Display Vertical Interrupt Register Vdvint 64. Video Display Vertical Interrupt Register VdvintVideo Display Field Bit Register Vdfbit FbitsetFbitclr VBITCLR1 VBITSET1Field† Symval† VBITCLR2 VBITSET2Field† Symval† Video Display Registers Recommended Values 34. Video Display Register Recommended ValuesRegister Field 525/60 Value 625/50 Value Vdfbit Fbitclr Fbitset VDVSYNS2 VSYNCXSTART2VDVSYNE2 VSYNCXSTOP2 VDVBIT1 VBITSET136. Video Display Fifo Registers Function Video Display Fifo Registers35. Video Display Fifo Registers Register BT.656 or Y/C Raw DataGeneral Purpose I/O Operation Gpio RegistersGpio Registers Video Port RegistersClass Revision Video Port Peripheral Identification Register VppidType ClassVideo Port Peripheral Control Register PCR Soft FreeStop PerenSoft CompPFUNC22 Video Port Pin Function Register PfuncVideo Port Pin Function Register Pfunc Field Descriptions NormalVDATA10TO19 PFUNC20PFUNC10 PFUNC0PDIR22 Video Port Pin Direction Register PdirVideo Port Pin Direction Register Pdir Field Descriptions VCTL3INVCTL2OUT PDIR21VCTL2IN PDIR20VDATA8TO9OUT PDIR8VDATA8TO9IN PDIR4PDIN12 Video Port Pin Data Input Register PdinPDIN20 PDIN7 PDIN6Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Output Register Pdout Video Port Pin Data Out Register Pdout Field Descriptions PDOUT21PDOUT20 Video Port Pin Data Set Register Pdset Video Port Pin Data Set Register Pdset Field Descriptions PDSET21PDSET20 Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register PdclrVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien Video Port Pin Interrupt Enable Register PienPIEN21 PIEN20PIPOL17 PIPOL16 PIPOL15 Video Port Pin Interrupt Polarity Register PipolPIPOL21 PIPOL20 PIPOL19 PIPOL13 PIPOL12VCTL3ACTLO PIPOL22VCTL3ACTHI PIPOL21Video Port Pin Interrupt Status Register Pistat VCTL2INT PISTAT22VCTL3INT PISTAT20Video Port Pin Interrupt Clear Register Piclr PICLR4PICLR22 PICLR21PICLR20 Vcxo Interpolated Control Port Overview Interface VIC Port Interface SignalsVIC Port Signal Direction Description Operational DetailsExample Values for Interpolation Rate Enabling VIC Port VIC Port RegistersVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field DescriptionsGO bit can be written to at any time VIC Input Register Vicin VIC Input Register Vicin Field DescriptionsVicinbits VIC Clock Divider Register Vicdiv VIC Clock Divider Register Vicdiv Field DescriptionsVicclkdiv Video Port Configuration Examples Example 1 Noncontinuous Frame Capture for 525/60 Format VCAIMGHSIZE2 * VCAIMGVSIZE2Frame VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1 VPVCASTRT1SSEENABLE, VCAXSTART1 Vpvcactlblkcapclear SPRU629 Vcayedmafrmcnt Edmaoptrmk Edmaoptprimedium Example 2 Noncontinuous Frame Display for 525/60 Format Vdhblnkstop Vdhblnkstart +Define vertical blanking bitVDVBITn reg values VDIMGHSIZE1 * VDIMGVSIZE1 Dmode VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2 Vpvdstatfrmdclear Vdyedmafrmcnt Vdyedmaelecnt Example 2 Noncontinuous Frame Display for 525/60 Format EDMAOPT2DSYES Index Index-2 Index-3 Pin data set register Pdset Pin direction register Pdir Vcaevtct Vdhblnk Index-7 Vddefval Vddispevt Index-9 Ydsta Ydstb