BT.656 and Y/C Mode Field and Frame Operation

Table 3–6. BT.656 and Y/C Mode Capture Operation

 

VCxCTL Bit

 

 

 

 

 

 

 

CON

FRAME

CF2

CF1

Operation

 

 

 

 

 

0

0

0

0

Reserved

0

0

0

1

Noncontinuous field 1 capture. Capture only field 1. F1C is set after

 

 

 

 

field 1 capture and causes CCMPx to be set. The F1C bit must be

 

 

 

 

cleared by the DSP before capture can continue. (The DSP has the

 

 

 

 

entire field 2 time to clear F1C before next field 1 begins.) Can also be

 

 

 

 

used for single progressive frame capture. (The DSP has vertical

 

 

 

 

blanking time to clear F1C before next frame begins.)

0

0

1

0

Noncontinuous field 2 capture. Capture only field 2. F2C is set after

 

 

 

 

field 2 capture and causes CCMPx to be set. The F2C bit must be

 

 

 

 

cleared by the DSP before capture can continue. (The DSP has the

 

 

 

 

entire field 1 time to clear F2C before next field 2 begins.)

0

0

1

1

Noncontinuous field 1 and field 2 capture. Capture both fields. F1C is

 

 

 

 

set after field 1 capture and causes CCMPx to be set. The F1C bit must

 

 

 

 

be cleared by the DSP before another field 1 capture can occur. (The

 

 

 

 

DSP has the entire field 2 time to clear F1C before next field 1 begins.)

 

 

 

 

F2C is set after field 2 capture and causes CCMPx to be set. The F2C

 

 

 

 

bit must be cleared by the DSP before another field 2 capture can

 

 

 

 

occur. (The DSP has the entire field 1 time to clear F2C before next

 

 

 

 

field 2 begins.)

0

1

0

0

Noncontinuous frame capture. Capture both fields. FRMC is set after

 

 

 

 

field 2 capture and causes CCMPx to be set. Capture halts upon

 

 

 

 

completion of the next frame unless the FRMC bit is cleared. (The DSP

 

 

 

 

has the entire next frame time to clear FRMC.)

0

1

0

1

Noncontinuous progressive frame capture. Capture field 1. FRMC is set

 

 

 

 

after field 1 capture and causes CCMPx to be set. Capture halts upon

 

 

 

 

completion of the next frame unless the FRMC bit is cleared. (The DSP

 

 

 

 

has the entire next frame time to clear FRMC.)

0

1

1

0

Reserved

0

1

1

1

Single frame capture. Capture both fields. FRMC is set after field 2

 

 

 

 

capture and causes CCMPx to be set. Capture halts until the FRMC bit

 

 

 

 

is cleared. (The DSP has the field 2 to field 1 vertical blanking time to

 

 

 

 

clear FRMC.)

1

0

0

0

Reserved

1

0

0

1

Continuous field 1 capture. Capture only field 1. F1C is set after field 1

 

 

 

 

capture and causes CCMPx to be set (CCMPx interrupt can be

 

 

 

 

disabled). The video port continues capturing field 1 fields, regardless

 

 

 

 

of the state of F1C.

 

 

 

 

 

3-18

Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual BT.656 and Y/C Mode Capture Operation, VC xCTL Bit
Page 79 Page 81

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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