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Texas Instruments TMS320C64x DSP manual DMA Operation, Capture DMA Event Generation

Models: TMS320C64x DSP

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DMA Operation

2.3 DMA Operation

The video port uses up to three DMA events per channel for a total of six possible events. Each DMA event uses a dedicated event output. The outputs are:

-VPYEVTA

-VPCbEVTA

-VPCrEVTA

-VPYEVTB

-VPCbEVTB

-VPCrEVTB

2.3.1Capture DMA Event Generation

Capture DMA events are generated based on the state of the capture FIFO(s). If no DMA event is currently pending and the FIFO crosses the value specified by VCTHRLDn, a DMA event is generated. Once an event has been requested, another DMA event may not be generated until the servicing of the outstanding event has begun (as indicated by the first read of the FIFO by the DMA event service). If the capture FIFO level exceeds 2⋅ the VCTHRLDn value before the requested DMA event completes, then another DMA event may be generated. Thus, up to one DMA event may be outstanding.

An outgoing data counter counts data read by the DMA. This counter is loaded with the VCTHRLDn value whenever a new DMA service begins. The counter then counts down for each double-word read from the FIFO by the DMA. The DMA is complete when the counter reaches zero. Figure 2–1 shows the capture DMA event generation.

For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb, and Cr color components. Each FIFO generates its own DMA event; therefore, the DMA event state and FIFO thresholds for each FIFO are tracked indepen- dently. The Cb and Cr FIFOs use a threshold value of

½(VCTHRLDn + VCTHRLDn mod 2).

2-6

Video Port

SPRU629

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Texas Instruments TMS320C64x DSP manual DMA Operation, Capture DMA Event Generation
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.