Displaying Video in Raw Data Mode

22)If continuous display is enabled, the video port begins displaying again at the start of the next field or frame. If noncontinuous field 1 and field 2 or frame display is enabled, the next field or frame is displayed, during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output.

4.11.1Handling Underrun Condition of the Display FIFO

A FIFO underrun occurs when the display FIFO is empty during an active display line because a pending DMA request failed to load the data in time. In case of a FIFO underrun condition, the DUND bit in VPIS is set. This condition initiates an interrupt to the DSP, if the underrun interrupt is enabled (the DUND bit in VPIE is set).

Because video display is typically a continuous real-time output, data output is not halted when a FIFO underrun occurs. (To output a blanking of default value is just as catastrophic to a display as outputting an old data value.) Instead, the FIFO read pointer continues to advance and (old) data continues to be output from the FIFO. This means that if the pending DMA is only slightly late, the data transfer has a chance to catch the FIFO back up to the read pointer and correct data output resumes. If the pending DMA does not complete service within a threshold’s worth of output data, then the DMA request sequence is broken and the remainder of the display field is corrupted.

The underrun interrupt routine should set the BLKDIS bit in VDCTL and it should reconfigure the DMA channel settings. Setting the BLKDIS bit flushes the channel display FIFO and prevents channel DMA events from reaching the DMA controller. The DMA must be reconfigured correctly for the next frame display since the current frame transfer failed. The frame line and frame pixel counters continue counting and, from a pin standpoint, the video display module appears to continue to function normally (SAV/EAV codes are generated in the BT.656 or Y/C mode and the default data value is sent out). The BLKDIS bit should then be cleared to reenable DMA events. Clearing the BLKDIS bit does not enable DMA events during the frame where the bit is cleared. Clearing this bit to zero enables DMA events in the frame that follows the frame where the bit is cleared.

SPRU629

Video Display Port

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Texas Instruments TMS320C64x DSP manual Handling Underrun Condition of the Display Fifo
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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