Display Timing Examples

4.9 Display Timing Examples

The following are examples of display output for several modes of operation.

4.9.1Interlaced BT.656 Timing Example

This section shows an example of BT.656 display output for a 704 ⋅ 408 inter- laced output image as might be generated by MPEG decoding.

The horizontal output timing is shown in Figure 4–33. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins. The actual delay can be longer or shorter as long as it is consistent within any display mode. The BT.656 active line is 720-pixels wide. Figure 4–33 shows the 704-pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels.

The HBLNK and HSYNC signals are shown as they would be output for active- low operation. Note that only one of the two signals is actually available exter- nally. The HBLNK inactive edge occurs either on sample 856 coincident with the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true BT.656 operation, neither HBLNK nor HSYNC would be used.

The IPCOUNT operation follows the description in section 4.1.2. IPCOUNT resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). The operation during nondisplay time is not a requirement, it could continue counting until the next FPCOUNT = IMGHOFFx point or it could reset immediately after IMGHSIZEx or when FPCOUNT is reset.

VDOUT shows the output data and switching between EAV, Blanking Data, SAV, Default Data, and FIFO Data. It is assumed that the DVEN bit in VDCTL is set to enable the default output.

SPRU629

Video Display Port

4-35

Page 179 Page 181
Page 180
Image 180
Texas Instruments TMS320C64x DSP manual Display Timing Examples, Interlaced BT.656 Timing Example
Page 179 Page 181

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
Top Page Image Contents