BT.656 and Y/C Mode Field and Frame Operation

3.4.3Horizontal Synchronization

Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line. The encoding of these bits is shown in Table 3–8.

Table 3–8. Horizontal Synchronization Programming

 

VCxCTL Bit

 

HMode

EXC

HRST

Horizontal Counter Reset Point

 

 

 

 

0

0

0

EAV code (H=1) – beginning of horizontal blanking.

1

0

1

SAV code (H=0) – Start of active video.

2

1

0

VCTL1 input active edge – beginning of horizontal blanking or horizontal

 

 

 

sync period. (VCTL1 must be configured as a horizontal control signal.)

3

1

1

VCTL1 input inactive edge – first active pixel on line or end of horizontal

 

 

 

sync. (VCTL1 must be configured as a horizontal control signal.)

 

 

 

 

HMode 0 is used for BT.656 or Y/C capture (with embedded control) and corre- sponds to the idea that each line begins with the horizontal blanking period. It does not align with most standards that start counting with the first active pixel; therefore, is only useful if capturing of HANC data before the SAV code is desired. HMode 1 is the default mode and corresponds to most digital video standards by making the first active pixel pixel0. It has the effect of associating horizontal blanking periods with the end of the previous line rather than the beginning of the line, but this is only an issue if you try to capture HANC data. In either mode, HCOUNT increments on every VCLKIN edge for Y/C operation and on every other VCLKIN edge for BT.656 operation but only when CAPEN is active. HCOUNT operation for HMode 0 and HMode 1 is shown in Figure 3–9.

HMode 2 and HMode 3 are used for BT.656 or Y/C capture without embedded EAV/SAV code and allow alignment with either the beginning of the horizontal blanking period or the first active pixel, or the beginning or end of horizontal sync depending on the VCTL1 input. When VCTL1 is configured as a horizontal control input, no external CAPEN signal is available so the CAPEN signal is considered to always be active. HCOUNT operation for HMode 3 and HMode 4 is shown in Figure 3–10 for VCTL1 operating as either HSYNC or AVID.

3-22

Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Horizontal Synchronization Programming, VCxCTL Bit HMode
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

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