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Texas Instruments TMS320C64x DSP manual Video Port Pin Interrupt Enable Register Pien

Models: TMS320C64x DSP

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GPIO Registers

5.1.9Video Port Pin Interrupt Enable Register (PIEN)

The video port pin interrupt enable register (PIEN) is shown in Figure 5–9 and described in Table 5–10. The GPIOs can be used to generate DSP interrupts or DMA events. The PIEN selects which pins may be used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set.

Interrupts are enabled on a GPIO pin when the corresponding bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR.

Figure 5–9.	Video Port		Pin Interrupt Enable Register (PIEN)
31									24

				Reserved

					R-0
23	22		21	20	19		18	17	16

Reserved	PIEN22		PIEN21	PIEN20		PIEN19	PIEN18	PIEN17	PIEN16

R-0	R/W-0		R/W-0	R/W-0		R/W-0	R/W-0	R/W-0	R/W-0
15	14		13	12	11		10	9	8

PIEN15	PIEN14		PIEN13	PIEN12		PIEN11	PIEN10	PIEN9	PIEN8

R/W-0	R/W-0		R/W-0	R/W-0		R/W-0	R/W-0	R/W-0	R/W-0
7	6		5	4	3		2	1	0

PIEN7	PIEN6		PIEN5	PIEN4		PIEN3	PIEN2	PIEN1	PIEN0

R/W-0	R/W-0		R/W-0	R/W-0		R/W-0	R/W-0	R/W-0	R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

SPRU629

General Purpose I/O Operation

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Texas Instruments TMS320C64x DSP manual Video Port Pin Interrupt Enable Register Pien

Contents

Literature Number SPRU629 April Important Notice Read This First Trademarks Contents Discusses operation of the video capture port Video Capture PortVCASTRT1, VCBSTRT1 VCASTOP1, VCBSTOP1VCASTRT2, VCBSTRT2 VCASTOP2, VCBSTOP211.1 VDVSYNE2 General Purpose I/O OperationVcxo Interpolated Control Port Figures Xii Figures Xiii Video Port Tables Xvi Tables Xvii Overview TopicVideo Port SPRU629 VCLK1 VCLK2 VCTL1 VCTL2 VCTL3Channel a Channel BVideo Port Fifo DMA InterfaceVideo Capture Fifo Configurations Ysrca Cbsrca Crsrca Ysrcb Cbsrcb CrsrcbYsrca Y/C Video Capture Fifo Configuration Ysrca Cbsrca CrsrcaVideo Display Fifo Configurations Ydsta Cbdst Crdst10-Bit Raw Video Display Fifo Configuration Ydsta Ydstb10. Y/C Video Display Fifo Configuration Video Port RegistersVideo Capture Signal Mapping Video Port Pin MappingVideo Display Signal Mapping Usage Raw Data Display ModeCapture Mode BT.656 Raw Data Data Bus 10-Bit 16-Bit 20-Bit ModeVdin Bus Usage for Capture Modes Vdin Data Bus Usage for Capture ModesVdout Data Bus Usage for Display Modes Vdout Data Bus Usage for Display ModesVideo Port Peripheral Bus Reset Reset OperationPower-On Reset Software Port Reset Capture Channel ResetDisplay Channel Reset Interrupt Operation DMA Operation Capture DMA Event GenerationCapture DMA Event Generation Flow Diagram Fifo ≥Display DMA Event Generation Display DMA Event Generation Flow Diagram DMA Size and Threshold Restrictions DMA Interface Operation Clocks Video Port Functionality SubsetsVideo Port Functional Clocks Data Bus WidthVideo Capture Throughput Video Port Throughput and LatencyFifo Size Y/C Video Capture Fifo Capacity Bit Bit Dense 10-BitBit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280 Video Display ThroughputRaw Video Display Fifo Capacity Acronym Register Name Section Video Port Control RegistersVideo Port Control Registers Video Port Control Register Vpctl Video Port Control Register Vpctl Field DescriptionsBit Value DescriptionNone Clear VCLK2PNone Reverse None ActivelowVpctl Bit Video Port Operating Mode SelectionOperating Mode Video Port Status Register Vpstat Video Port Status Register Vpstat Field DescriptionsVideo Port Interrupt Enable Register Vpie Dcna SerrbCcmpb Lfda Video Port Interrupt Status Register Vpis Dcna DcmpTick STC Lfda Sfda VINTA2 VINTA1 Serra Ccmpa CovraVcount = Ystop Vcbctl Out of the port. The DMA complete interrupt can be used to BT.656 or Y/C capture mode Lfda is set when long field Vcactl Video Capture Port TSI Bit Cmode Bits Mode Description Video Capture Mode SelectionVideo Capture Mode Selection BT.656 Video Capture Mode 1 BT.656 Capture Channels2 BT.656 Timing Reference Codes BT.656 Video Timing Reference CodesError Correction by Protection Bits BT.656 Protection BitsLine Information Bits Protection Bits Received F, V, and H BitsP 0 Bits 3 BT.656 Image Window and Capture010 011 100 101 Video Capture Parameters Common Video Source Parameters4 BT.656 Data Sampling 5 BT.656 Fifo Packing Bit BT.656 Fifo PackingVDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y Bit BT.656 Dense Fifo Packing 2 Y/C Timing Reference Codes Y/C Video Capture Mode1 Y/C Capture Channels 3 Y/C Image Window and Capture 4 Y/C Fifo Packing Bit Y/C Fifo PackingVDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing Bit Y/C Dense Fifo Packing BT.656 and Y/C Mode Field and Frame Operation Capture Determination and NotificationOperation BT.656 and Y/C Mode Capture OperationVC xCTL Bit Vertical Synchronization VCxCTL BitVC xCTL Bit VMode Vertical Counter Reset PointVertical Synchronization Programming Vcount Operation Example EXC = Horizontal Counter Reset Point Horizontal SynchronizationHorizontal Synchronization Programming VCxCTL Bit HModeHcount Operation Example EXC = Field Identification Field Identification ProgrammingField Detect Method EAV code11.Field 1 Detection Timing Short and Long Field Detect10. Input Filter Mode Selection Video Input FilteringInput Filter Modes Filter OperationChrominance Resampling Operation Scaling Operation13 /2 Scaled Co-Sited Filtering EAV Edge Pixel ReplicationSAV 16. Capture Window Not Requiring Edge Pixel Replication Xstart Xsize SAVVertical Ancillary Vanc Data Capture Ancillary Data CaptureHorizontal Ancillary Hanc Data Capture Raw Data Capture Mode Raw Data Capture Notification11. Raw Data Mode Capture Operation Raw Data Fifo Packing17 -Bit Raw Data Fifo Packing 19 -Bit Dense Raw Data Fifo Packing 21 -Bit Raw Data Fifo Packing TSI Data Capture TSI Capture ModeTSI Capture Features Vclkin Capen Pacstrt TSI Capture Error DetectionSynchronizing the System Clock PCR CtmodeVcactl Bit 12. TSI Capture Mode OperationTSI Data Capture Notification Writing to the Fifo VclkinTSI TSI Fifo PerrCapture Line Boundary Conditions Reading from the FifoIpcount = IMGHSIZE78 Vclkout FifoCapturing Video in BT.656 or Y/C Mode Handling Fifo Overrun in BT.656 or Y/C Mode Capturing Video in Raw Data Mode Capturing Data in TSI Capture Mode Handling Fifo Overrun Condition in Raw Data ModeHandling Fifo Overrun Condition in TSI Capture Mode Video Capture Registers 13. Video Capture Control RegistersVideo Capture Channel x Status Register VCASTAT, Vcbstat BT.656 or Y/C Mode Raw Data Mode TSI Mode Description BitDetected Value BT.656 or Y/C Mode Raw Data Mode TSI ModeVcfld Video Capture Channel a Control Register Vcactl Block RdfeFIELD1 FIELD2Eavfid FDLV1EAV V0EAVHalf CON ‡Description Raw Data Mode TSI Mode VCXSTART/VCVBLNKP VcystartSSE Vcxstart VcvblnkpVcystop VcxstopField† Symval† FFFh Last captured line Not used VIF2 FSCL2 VINT2VIF1 VINT1VIF2 SPRU629 VCTHRLD2 VCTHRLD1CAPEVTCT2 CAPEVTCT1CON Frame CF2 CF1 Video Capture Channel B Control Register VcbctlVrst Hrst Vcen PK10B Lfde Sfde Resmpl F1C, F2C, and Frmc status bits, in VCBSTAT, are not EAV or Not used VCTL1 active edge CON‡ Capture field Not usedTSI Capture Control Register Tsictl Enstc Tcken Sten CtmodeValue BT.656, Y/C Mode TSI Mode Or Raw Data Mode 24. TSI Capture Control Register Tsictl Field DescriptionsBT.656, Y/C Mode TSI Mode Or Raw Data Mode TSI Clock Initialization LSB Register TsiclkinitlInpcr Bit FieldInpcre TSI Clock Initialization MSB Register TsiclkinitmInpcrm TSI System Time Clock LSB Register Tsistclkl 42. TSI System Time Clock LSB Register TsistclklPcre TSI System Time Clock MSB Register TsistclkmPcre Pcrm TSI System Time Clock Compare LSB Register Tsistcmpl ATCTSI System Time Clock Compare MSB Register Tsistcmpm 45. TSI System Time Clock Compare MSB Register TsistcmpmTSI System Time Clock Compare Mask LSB Register Tsistmskl AtcmTSI System Time Clock Compare Mask MSB Register Tsistmskm TSI System Time Clock Ticks Interrupt Register Tsiticks TickctCapture Mode Register BT.656 or Y/C Raw Data Video Capture Fifo Registers34. Video Capture Fifo Registers 35. Video Capture Fifo Registers FunctionVideo Display Port Video Display Mode Selection Video Display Mode SelectionDmode Bits Mode Description Image TimingNtsc Compatible Interlaced Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Video Display CountersHorizontal Blanking and Horizontal Sync Timing FpcountSync Signal Generation FlcountVblnk VsyncExternal Sync Operation Port Sync OperationBT.656 Video Display Mode Display Timing Reference CodesBT.656 Frame Timing Line Number11.Digital Vertical F and V Transitions Blanking Codes 3 BT.656 Image Display4 BT.656 Fifo Unpacking 12 -Bit BT.656 Fifo Unpacking13 -Bit BT.656 Fifo Unpacking 14. BT.656 Dense Fifo Unpacking Y/C Video Display Mode 1 Y/C Display Timing Reference Codes4 Y/C Fifo Unpacking 2 Y/C Blanking Codes3 Y/C Image Display 16 -Bit Y/C Fifo Unpacking 17 -Bit Y/C Fifo Unpacking 18 -Bit Y/C Dense Fifo Unpacking Output Filter Mode Selection Video Output FilteringOutput Filter Modes Vdctl Bit19. Chrominance Resampling 20 x Co-Sited Scaling 23. Luma Edge Replication Raw Data Display Mode Ancillary Data DisplayHorizontal Ancillary Hanc Data Display Vertical Ancillary Vanc Data DisplayRaw Mode RGB Output Support Raw Data Fifo Unpacking26 -Bit Raw Fifo Unpacking 28 -Bit Raw Fifo Unpacking 30 -Bit Raw 3/4 Fifo Unpacking Video Display Field and Frame Operation Display Determination and NotificationDisplay Operation CON Frame DF2 DF1Video Display Event Generation Display Line Boundary Conditions 32. Display Line Boundary Example Display Timing Examples Interlaced BT.656 Timing Example33. BT.656 Interlaced Display Horizontal Timing Example SPRU629 34. BT.656 Interlaced Display Vertical Timing Example Interlaced Raw Display Example 35. Raw Interlaced Display Horizontal Timing SPRU629 36. Raw Interlaced Display Vertical Timing Example 3 Y/C Progressive Display Example 37. Y/C Progressive Display Horizontal Timing Example SPRU629 38. Y/C Progressive Display Vertical Timing Example Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode Handling Underrun Condition of the Display Fifo Video Display Registers Video Display Control RegistersVideo Display Status Register Vdstat Video Display Status Register Vdstat Field Descriptions Video Display Control Register Vdctl Field Descriptions BT.656 and Y/C Mode Raw Data ModeVideo Display Control Register Vdctl Disable Enable BlkdisFXS OutputValue BT.656 and Y/C Mode Raw Data Mode Rgbx BlankingFrmdis FlddisFrmwidth Video Display Frame Size Register VdfrmszFrmheight Video Display Horizontal Blanking Register Vdhblnk HbdlaHblnkstart DelayHblnkstop VBLNKYSTART1 VBLNKXSTART1VBLNKYSTOP1 VBLNKXSTOP1Field† Symval† VBLNKYSTART2 VBLNKXSTART2VBLNKYSTOP2 VBLNKXSTOP2Video Display Field 1 Image Offset Register VDIMGOFF1 Negoff IMGVOFF1IMGHOFF1 IMGHSIZE1 Video Display Field 1 Image Size Register VDIMGSZ1IMGVSIZE1 IMGHOFF2 Video Display Field 2 Image Offset Register VDIMGOFF2IMGVOFF2 None IMGHSIZE2 Video Display Field 2 Image Size Register VDIMGSZ2IMGVSIZE2 FLD1XSTART Video Display Field 1 Timing Register VDFLDT1FLD1YSTART FLD2XSTART Video Display Field 2 Timing Register VDFLDT2FLD2YSTART Video Display Threshold Register Vdthrld IncpixVDTHRLD2 VDTHRLD1Hsyncstart Video Display Horizontal Synchronization Register VdhsyncHsyncstop VSYNCYSTART1 VSYNCXSTART1VSYNCYSTOP1 VSYNCXSTOP1VSYNCYSTART2 VSYNCXSTART2VSYNCYSTOP2 VSYNCXSTOP2Video Display Counter Reload Register Vdreload VrldHrld CrldDISPEVT1 Video Display Display Event Register VddispevtDISPEVT2 Video Display Clipping Register Vdclip ClipchighClipyhigh Clipylow ClipclowYdefval Video Display Default Display Value Register VddefvalCrdefval Cbdefval Defval CrdefvalVideo Display Vertical Interrupt Register Vdvint 64. Video Display Vertical Interrupt Register VdvintFbitclr Video Display Field Bit Register VdfbitFbitset VBITCLR1 VBITSET1Field† Symval† VBITCLR2 VBITSET2Field† Symval† Register Field 525/60 Value 625/50 Value Video Display Registers Recommended Values34. Video Display Register Recommended Values VDVSYNS2 VSYNCXSTART2 VDVSYNE2 VSYNCXSTOP2Vdfbit Fbitclr Fbitset VDVBIT1 VBITSET1Video Display Fifo Registers 35. Video Display Fifo Registers36. Video Display Fifo Registers Function Register BT.656 or Y/C Raw DataGeneral Purpose I/O Operation Gpio RegistersGpio Registers Video Port RegistersVideo Port Peripheral Identification Register Vppid TypeClass Revision ClassVideo Port Peripheral Control Register PCR Soft FreePeren SoftStop CompVideo Port Pin Function Register Pfunc Video Port Pin Function Register Pfunc Field DescriptionsPFUNC22 NormalPFUNC20 PFUNC10VDATA10TO19 PFUNC0Video Port Pin Direction Register Pdir Video Port Pin Direction Register Pdir Field DescriptionsPDIR22 VCTL3INPDIR21 VCTL2INVCTL2OUT PDIR20PDIR8 VDATA8TO9INVDATA8TO9OUT PDIR4Video Port Pin Data Input Register Pdin PDIN20PDIN12 PDIN7 PDIN6Video Port Pin Data Input Register Pdin Field Descriptions Video Port Pin Data Output Register Pdout PDOUT20 Video Port Pin Data Out Register Pdout Field DescriptionsPDOUT21 Video Port Pin Data Set Register Pdset PDSET20 Video Port Pin Data Set Register Pdset Field DescriptionsPDSET21 Video Port Pin Data Clear Register Pdclr Video Port Pin Data Clear Register PdclrVideo Port Pin Data Clear Register Pdclr Field Descriptions Video Port Pin Interrupt Enable Register Pien Video Port Pin Interrupt Enable Register PienPIEN21 PIEN20Video Port Pin Interrupt Polarity Register Pipol PIPOL21 PIPOL20 PIPOL19PIPOL17 PIPOL16 PIPOL15 PIPOL13 PIPOL12PIPOL22 VCTL3ACTHIVCTL3ACTLO PIPOL21Video Port Pin Interrupt Status Register Pistat PISTAT22 VCTL3INTVCTL2INT PISTAT20Video Port Pin Interrupt Clear Register Piclr PICLR4PICLR20 PICLR22PICLR21 Vcxo Interpolated Control Port Overview VIC Port Interface Signals VIC Port Signal Direction DescriptionInterface Operational DetailsExample Values for Interpolation Rate VIC Port Registers Enabling VIC PortVIC Port Registers VIC Control Register Vicctl VIC Control Register Vicctl Field DescriptionsGO bit can be written to at any time Vicinbits VIC Input Register VicinVIC Input Register Vicin Field Descriptions Vicclkdiv VIC Clock Divider Register VicdivVIC Clock Divider Register Vicdiv Field Descriptions Video Port Configuration Examples Example 1 Noncontinuous Frame Capture for 525/60 Format VCAIMGHSIZE2 * VCAIMGVSIZE2Frame VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1 VPVCASTRT1SSEENABLE, VCAXSTART1 Vpvcactlblkcapclear SPRU629 Vcayedmafrmcnt Edmaoptrmk Edmaoptprimedium Example 2 Noncontinuous Frame Display for 525/60 Format Vdhblnkstop Vdhblnkstart +Define vertical blanking bitVDVBITn reg values VDIMGHSIZE1 * VDIMGVSIZE1 Dmode VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2 Vpvdstatfrmdclear Vdyedmafrmcnt Vdyedmaelecnt Example 2 Noncontinuous Frame Display for 525/60 Format EDMAOPT2DSYES Index Index-2 Index-3 Pin data set register Pdset Pin direction register Pdir Vcaevtct Vdhblnk Index-7 Vddefval Vddispevt Index-9 Ydsta Ydstb