4-

Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example

 

 

 

 

 

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Video

VCLKIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

268

 

4

 

 

 

 

 

1440

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Display

 

 

 

 

 

 

One Line

 

 

 

 

 

 

 

 

 

Next Line

IPCOUNT

703 703 703

703

703 703

703

703

703 703 703 703 703

703

0

1

2

702 703 703

703 703 703 703

 

FPCOUNT

720 721

722

723

735 736

799

800

855 856

857 0

1

7

8

9

10

710 711 712

718 719

720 721

Port

VCTL1 (HBLNK)† §

 

 

 

 

 

 

 

 

‡

 

 

 

 

 

 

 

 

VCTL1 (HSYNC)† §

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCLKOUT

Display Image

Blanking Active Video

Display Timing Examples

VDOUT[9–0]

 

 

DefCr

 

DefY

 

FF.C

 

00.0

 

00.0

 

XY.0

 

80.0

 

10.0

 

80.0

 

10.0

 

 

80.0

 

10.0

 

80.0

 

10.0

 

FF.C

 

00.0

 

00.0

 

XY.0

 

DefCb

 

DefY

 

DefCr

 

DefY

 

 

 

DefCr

 

DefY

 

Cb0

 

Y0

 

Cr0

 

Y1

 

Cb1

 

Y2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EAV Blanking Data

 

 

 

 

 

 

 

 

 

 

 

SAV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FLCOUNT

n – 1

 

 

 

 

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FRMWIDTH = 858

IMGHOFF1 = 8

HSYNCSTART = 736

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HBLNKSTART = 720

IMGHSIZE1 = 704

HSYNCSTOP = 800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HBLNKSTOP = 856

IMGHOFF2 = 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IMGHSIZE2 = 704

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

†Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.

‡ HBLNK operation when HBDLA bit in VDHBLNK is set to 1.

§ Diagram assumes a two VCLK pipeline delay between internal counters and output signals.

Cb351

Y702

Cr351

Y703

Def Cb

Def Y

CbDef YDef CrDef YDefFF.C00.000.0XY.0

EAV

n + 1

SPRU629

Page 180 Page 182
Page 181
Image 181
Texas Instruments TMS320C64x DSP manual 33. BT.656 Interlaced Display Horizontal Timing Example
Page 180 Page 182

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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