Video Port Throughput and Latency

2.6.2Video Display Throughput

Video display throughput may be calculated in a manner similar to video capture. In this case, the time to fill the display FIFO must be less than the time to empty the FIFO or underflow occurs. The 110 MHz display rate supports a maximum display resolution of 1280 ⋅ 1024 at 63 Hz (frame rate). This means that the horizontal blanking time is ~3.88 ∝ s. The time to empty a completely full FIFO may be represented by the formula tE + n(tH), where tE is the time to empty the FIFO of active samples, tH is the horizontal blanking time, and n is the number of lines of active video that the FIFO can hold. In raw display mode, the FIFO is 5120 bytes. The number of samples that the buffer can hold depends on the buffer packing mode as listed in Table 2–3.

Table 2–3. Raw Video Display FIFO Capacity

 

8-Bit

10-Bit Dense

10/16-Bit

20-Bit

Samples

5120

3840

2560

1280

 

 

 

 

 

Using these values and the formula above, the maximum time to fill the FIFO (tI) may be calculated for each case. The DMA input rate (rI) is then calculated as the FIFO size divided by tI:

8-bit (n=4):

tI < tE + n(tH)

 

tI < 5120/110 MHz + 4(3.88 ∝ s)

 

tI < 62.6 ∝ s

 

rI = tI/5120 = 12.12 ns (82.5 MBytes/s)

10-bit dense (n=3):

tI < tE + n(tH)

 

tI < 3840/110 MHz + 3(3.88 ∝ s)

 

tI < 46.55 ∝ s

 

rI = tI/5120 = 9.09 ns (110 MBytes/s)

16-bit (n=2):

tI < tE + n(tH)

 

tI < 2560/110 MHz + 2(3.88 ∝ s)

 

tI < 31.03 ∝ s

 

rI = tI/5120 = 6.06 ns (165 MBytes/s)

20-bit (n=1):

tI < tE + n(tH)

 

tI < 1280/110 MHz + 1(3.88 ∝ s)

 

tI < 15.52 ∝ s

 

rI = tI/5120 = 3.03 ns (330 MBytes/s)

SPRU629

Video Port

2-15

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Texas Instruments TMS320C64x DSP manual Video Display Throughput, Raw Video Display Fifo Capacity
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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