Example 2: Noncontinuous Frame Display for 525/60 Format

A.2 Example 2: Noncontinuous Frame Display for 525/60 Format

This is an example that explains how to configure the video port for 8-bit BT.656 noncontinuous frame display for 525/60 format. See ITU–R BT.656–4 and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for more details on 525/60 format. For simplicity, this example does not contain any margins; that is, both vertical and horizontal offsets are zero. In other words, both active area and image area are the same.

/**********************************************************/ /* Display parameter definitions based on 525/60 format */ /**********************************************************/

/* ––––––––––––––––– */ /* Define frame size */ /* ––––––––––––––––– */ #define VD_FRM_WIDTH

#define VD_FRM_HEIGHT #define VD_FRM_SIZE

/* ––––––––––––––––––– */ /* Horizontal blanking */ /* ––––––––––––––––––– */ #define VD_HBLNK_START #define VD_HBLNK_STOP #define VD_HBLNK_SIZE

858

/* no of pixels per frame line

*/

 

/* including horizontal blanking

*/

525

/* total noof lines per frame

*/

(VD_FRM_WIDTH * VD_FRM_HEIGHT)

720

/* starting location of EAV

*/

856

/* starting location of SAV

*/

(VD_HBLNK_STOP – VD_HBLNK_START +

 

2/*EAV*/) /* (138) EAV, SAV inclusive */

/* –––––––––––––––––––––––––––– */

 

/* Vertical blanking for field1 */

 

/* –––––––––––––––––––––––––––– */

 

#define VD_VBLNK_XSTART1

720

/* pixel on which VBLNK active

*/

 

 

/* edge occurs for field1

*/

#define VD_VBLNK_YSTART1

1 /* line on which VBLNK active

*/

 

 

/* edge occurs for field1

*/

#define VD_VBLNK_XSTOP1

720

/* pixel on which VBLNK inactive

*/

 

 

/* edge occurs for field1

*/

#define VD_VBLNK_YSTOP1

20

/* line on which VBLNK inactive

*/

 

 

/* edge occurs for field1

*/

/* –––––––––––––––––––––––––––– */

 

/* Vertical blanking for field2 */

 

/* –––––––––––––––––––––––––––– */

 

#define VD_VBLNK_XSTART1

360

/* pixel on which VBLNK active

*/

 

 

/* edge occurs for field2

*/

#define VD_VBLNK_YSTART1

263

/* line on which VBLNK active

*/

 

 

/* edge occurs for field2

*/

#define VD_VBLNK_XSTOP1

360

/* pixel on which VBLNK inactive

*/

 

 

/* edge occurs for field2

*/

#define VD_VBLNK_YSTOP1

283

/* line on which VBLNK inactive

*/

 

 

/* edge occurs for field2

*/

A-10

Video Port Configuration Examples

SPRU629

Page 286
Image 286
Texas Instruments TMS320C64x DSP manual Example 2 Noncontinuous Frame Display for 525/60 Format, Vdhblnkstop Vdhblnkstart +

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.