Video Display Registers

4.12.26 Video Display Field Bit Register (VDFBIT)

The video display field bit register (VDFBIT) controls the F bit value in the EAV and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and described in Table 4–31.

The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV timing control codes. The F bit is cleared to 0 (indicating field 1 display) in the EAV code at the beginning of the line whenever the frame line counter (FLCOUNT) is equal to FBITCLR. It remains a 0 for all subsequent EAV/SAV codes until the EAV at the beginning of the line when FLCOUNT = FBITSET where it changes to 1 (indicating field 2 display). The F bit operation is completely inde- pendent of the FLD control signal.

For interlaced operation, FBITCLR and FBITSET are typically programmed such that the F bit changes coincidently with or some time after the V bit transi- tions from 1 to 0 (as determined by VBITCLR1 and VBITCLR2 in VDVBITn). For progressive scan operation no field 2 output occurs, so FBITSET should be programmed to a value greater than FRMHEIGHT so that the condition FLCOUNT = FBITSET never occurs and the F bit is always 0.

Figure 4–65. Video Display Field Bit Register (VDFBIT)

31

 

28

27

 

 

16

 

Reserved

 

 

 

FBITSET

 

 

 

 

 

 

 

 

 

R-0

 

 

 

R/W-0

 

15

 

12

11

 

 

0

 

 

 

 

 

 

 

 

Reserved

 

 

 

FBITCLR

 

 

 

 

 

 

 

 

 

R-0

 

 

 

R/W-0

 

Legend: R = Read only; R/W = Read/Write; -n= value after reset

 

Table 4–31. Video Display Field Bit Register (VDFBIT) Field Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

Bit

field†

symval†

Value

BT.656 and Y/C Mode

Raw Data Mode

31–28

Reserved

–

 

0

Reserved. The reserved bit location is always read as 0. A

 

 

 

 

 

value written to this field has no effect.

 

 

 

 

 

 

 

27–16

FBITSET

OF(value)

0–FFFh

Specifies the first line with an EAV of

Not used.

 

 

 

 

 

F = 1 indicating field 2 display.

 

 

 

 

 

 

 

 

15–12

Reserved

–

 

0

Reserved. The reserved bit location is always read as 0. A

 

 

 

 

 

value written to this field has no effect.

 

 

 

 

 

 

 

11–0

FBITCLR

OF(value)

0–FFFh

Specifies the first line with an EAV of

Not used.

 

 

 

 

 

F = 0 indicating field 1 display.

 

 

 

 

 

 

 

 

† For CSL implementation, use the notation VP_VDFBIT_field_symval

SPRU629

Video Display Port

4-89

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Texas Instruments TMS320C64x DSP manual Video Display Field Bit Register Vdfbit, Fbitset, Fbitclr
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

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In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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