Video Display Field and Frame Operation

Table 4–4. Display Operation (Continued)

 

VDCTL Bit

 

 

CON

FRAME

DF2

DF1

Operation

 

 

 

 

 

1

0

1

0

Continuous field 2 display. Display only field 2. F2D is set after field 2

 

 

 

 

display and causes DCMPx to be set (DCMPx interrupt can be dis-

 

 

 

 

abled). No DCNA interrupt occurs, regardless of the state of F2D.

1

0

1

1

Reserved

1

1

0

0

Continuous frame display. Display both fields. FRMD is set after field 2

 

 

 

 

display and causes DCMPx to be set (DCMPx interrupt can be dis-

 

 

 

 

abled. No DCNA interrupt occurs, regardless of the state of FRMD.

1

1

0

1

Continuous progressive frame display. Display field 1. FRMD is set af-

 

 

 

 

ter field 1 display and causes DCMPx to be set (DCMPx interrupt can

 

 

 

 

be disabled). No DCNA interrupt occurs, regardless of the state of

 

 

 

 

FRMD. (Functions identically to continuous field 1 display mode except

 

 

 

 

the FRMD bit is used instead of the F1D bit.) If external control signals

 

 

 

 

are used, they must follow progressive format.

1

1

1

0

Reserved

1

1

1

1

Reserved

 

 

 

 

 

4.7.2Video Display Event Generation

The display FIFOs are filled using DMAs as requested by the video port DMA events. The VDTHRLD value indicates the level at which the FIFO has enough room to receive another DMA block of data. Depending on the size of the DMA, the FIFO may have room for multiple transfers before reaching the VDTHRLD level. Once the threshold is reached, another DMA event is generated as soon as the FIFO again falls below the VDTHRLD level.

Once an entire field worth of data has been sent to the FIFO, the video port may need to stop generating events in order to allow the DSP to change DMA. Since display may not yet be complete (the FIFO continues to empty after falling below VDTHRLD), a display event counter (DEVTCT) is provided to track the number of requested YEVT events. The counter is loaded with the number of events needed in a display field (DISPEVT1 or DISPEVT2) and is decremented each time the event is requested. Once the counter reaches 0, further display events are inhibited. At the start of the next field, DEVTCT is reloaded and display events are reenabled.

4-32

Video Display Port

SPRU629

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Texas Instruments TMS320C64x DSP manual Video Display Event Generation
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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