Video Capture Registers

Table 3–24. TSI Capture Control Register (TSICTL) Field Descriptions

 

 

 

 

 

 

Description

Bit

field†

symval†

Value

BT.656, Y/C Mode,

 

TSI Mode

or Raw Data Mode

 

31–6

Reserved

–

0

Reserved. The reserved bit location is always read as 0. A value

 

 

 

 

written to this field has no effect.

 

 

 

 

 

 

5

ENSTC

 

 

System time clock enable bit.

 

 

HALTED

0

Not used.

 

System time clock input is disabled (to

 

 

 

 

 

 

 

 

 

save power). The system time clock

 

 

 

 

 

 

counters and tick counter do not increment.

 

 

CLKED

1

Not used.

 

System time input is enabled. The system

 

 

 

 

 

 

time clock counters and tick counters are

 

 

 

 

 

 

incremented by STCLK.

 

 

 

 

 

 

4

TCKEN

 

 

Tick count interrupt enable bit.

 

 

DISABLE

0

Not used.

 

Setting of the TICK bit is disabled.

 

 

 

 

 

SET

1

Not used.

 

The TICK bit in VPIS is set whenever the

 

 

 

 

 

 

tick count is reached.

 

 

 

 

 

 

 

3

STEN

 

 

System time clock interrupt enable bit.

 

 

DISABLE

0

Not used.

 

Setting of the STC bit is disabled.

 

 

 

 

 

SET

1

Not used.

 

A valid STC compare sets the STC bit in

 

 

 

 

 

 

VPIS.

 

 

 

 

 

 

 

2

CTMODE

 

 

Counter mode select bit.

 

 

90KHZ

0

Not used.

 

The 33-bit PCR portion of the system time

 

 

 

 

 

 

 

 

 

counter increments at 90 kHz (when PCRE

 

 

 

 

 

 

rolls over from 299 to 0).

 

 

STCLK

1

Not used.

 

The 33-bit PCR portion of the system time

 

 

 

 

 

 

counter increments by the STCLK input.

 

 

 

 

 

 

 

1

ERRFILT

 

 

Error filtering enable bit.

 

 

ACCEPT

0

Not used.

 

Packets with errors are received and the

 

 

 

 

 

 

 

 

 

PERR bit is set in the timestamp inserted at

 

 

 

 

 

 

the end of the packet.

 

 

REJECT

1

Not used.

 

Packets with errors are filtered out (not

 

 

 

 

 

 

received in the FIFO).

 

 

 

 

 

 

 

0

Reserved

–

0

Reserved. The reserved bit location is always read as 0. A value

 

 

 

 

written to this field has no effect.

 

 

 

 

 

 

 

† For CSL implementation, use the notation VP_TSICTL_field_symval

SPRU629

Video Capture Port

3-73

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Texas Instruments TMS320C64x DSP manual TSI Capture Control Register Tsictl Field Descriptions
Page 134 Page 136

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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