Capture Line Boundary Conditions

In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When the condition HCOUNT = VCXSTOP occurs, the FIFO location is written even though 8 bytes have not been received. The next capture line then begins in the next FIFO location at byte 0. This operation extends to all capture modes. In the case of TSI and raw data modes, there are no lines. In these modes, a final write at the end of the packet must be performed when the packet data count equals the 24-bit combined value of VCXCOUNT and VCYCOUNT.

Figure 3–28. Capture Line Boundary Example

 

 

 

 

 

 

 

 

 

 

 

 

 

IPCOUNT = IMGHSIZE(78)

 

 

 

VCLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDOUT[9–2]

Y 72

Y73

Y 74

Y 75

Y 76

Y 77

YDEF YDEF YDEF YDEF YDEF YDEF

 

VDOUT[19–12]

Cb 36

Cr 36

Cb 37

Cr 37

Cb 38

Cr 38 CbDEFCrDEFCbDEFCrDEFCbDEFCrDEF

 

63

56 55

 

48 47

 

40 39

32 31

 

24 23

16 15

8 7

0

 

Y 7

Y 6

 

Y 5

 

Y 4

 

Y 3

Y 2

Y 1

Y 0

 

Y 71

Y 70

 

Y 77

 

Y 76

 

Y 75

Y 74

Y 73

Y 72

Y FIFO

 

Y 69

 

Y 68

 

Y 67

Y 66

Y 65

Y 64

 

63

56 55

 

48 47

 

40 39

3231

 

24 23

16 15

8 7

0

 

 

 

Cb 7

 

Cb 6

 

Cb 5

 

Cb 4

 

Cb 3

 

Cb 2

 

Cb 1

 

Cb 0

 

 

 

 

 

Cb 38

 

Cb 37

 

Cb 36

 

Cb 35

 

Cb 34

 

Cb 33

 

Cb 32

Cb FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

56 55

48 47

40 39

3231

24 23

16 15

8 7

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cr 7

 

Cr 6

 

Cr 5

 

Cr 4

 

Cr 3

 

Cr 2

 

Cr 1

 

Cr 0

 

 

 

 

 

Cr 38

 

Cr 37

 

Cr 36

 

Cr 35

 

Cr 34

 

Cr 33

 

Cr 32

Cr FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Little-Endian Packing

 

 

 

 

 

63

56 55

48 47

40 39

32 31

24 23

16 15

8 7

0

 

 

 

Y 0

 

Y 1

 

Y 2

 

Y 3

 

Y 4

 

Y 5

 

Y 6

 

Y 7

 

 

 

Y 72

 

Y 73

 

Y 74

 

Y 75

 

Y 76

 

Y 77

 

 

 

 

 

 

 

 

 

 

Y FIFO

 

Y 64

 

Y 65

 

Y 66

 

Y 67

 

Y 68

 

Y 69

 

Y 70

 

Y 71

 

 

 

 

 

 

 

 

 

 

 

 

 

63

56 55

48 47

40 39

3231

24 23

16 15

8 7

0

 

 

 

Cb 0

 

Cb 1

 

Cb 2

 

Cb 3

 

Cb 4

 

Cb 5

 

Cb 6

 

Cb 7

 

 

 

Cb 32

 

Cb 33

 

Cb 34

 

Cb 35

 

Cb 36

 

Cb 37

 

Cb 38

 

 

Cb FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

56 55

48 47

40 39

3231

24 23

16 15

8 7

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cr 0

 

Cr 1

 

Cr 2

 

Cr 3

 

Cr 4

 

Cr 5

 

Cr 6

 

Cr 7

Cr FIFO

 

Cr 32

 

Cr 33

 

Cr 34

 

Cr 35

 

Cr 36

 

Cr 37

 

Cr 38

 

 

 

 

 

 

 

 

Big-Endian Packing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Line n+1 Line n

Line n+1 Line n

Line n+1 Line n

Line n+1 Line n

Line n+1 Line n

Line n+1 Line n

SPRU629

Video Capture Port

3-43

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Image 105
Texas Instruments TMS320C64x DSP manual Ipcount = IMGHSIZE78 Vclkout, Fifo
Page 104 Page 106

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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