Bit Raw Fifo Unpacking | Texas Instruments TMS320C64x DSP specs

Raw Data Display Mode

Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked from each word of the FIFO.

Figure 4–28. 16-Bit Raw FIFO Unpacking

VCLKOUT

VDOUT[19–12]/VDOUT[9–2]		Raw 0 Raw 1 Raw 2 Raw 3		Raw 4 Raw 5 Raw 6 Raw 7		Raw 8 Raw 9	Raw 10 Raw 11
63		4847		3231		1615	0
	Raw 11		Raw 10		Raw 9		Raw 8
	Raw 7		Raw 6		Raw 5		Raw 4
	Raw 3		Raw 2		Raw 1		Raw 0
	Raw 3		Raw 2		Raw 1		Raw 0
Raw FIFO			Little-Endian Unpacking
			Little-Endian Unpacking
63		4847		3231		1615	0
	Raw 8		Raw 9		Raw 10		Raw 11
	Raw 4		Raw 5		Raw 6		Raw 7
	Raw 0		Raw 1		Raw 2		Raw 3
	Raw 0		Raw 1		Raw 2		Raw 3

Raw FIFO	Big-Endian Unpacking

The FIFO unpacking for 20-bit raw format is shown in Figure 4–29. One sample is unpacked from each word of the FIFO.

Figure 4–29. 20-Bit Raw FIFO Unpacking

Y FIFO

VCLKOUT

VDOUT[19–0]	Raw 0 Raw 1 Raw 2 Raw 3	Raw 4 Raw 5 Raw 6 Raw 7	Raw 8 Raw 9	Raw 10 Raw 11
63	5251	3231	2019	0
	Raw 7			Raw 6
	Raw 5			Raw 4
	Raw 3			Raw 2
	Raw 1			Raw 0
		Little-Endian Unpacking
63	5251	3231	2019	0
	Raw 6			Raw 7
	Raw 4			Raw 5
	Raw 2			Raw 3
	Raw 0			Raw 1

Big-Endian Unpacking

4-28

Video Display Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Bit Raw Fifo Unpacking

Models: TMS320C64x DSP

Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked from each word of the FIFO.

Figure 4–28. 16-Bit Raw FIFO Unpacking

Figure 4–29. 20-Bit Raw FIFO Unpacking

Y FIFO

TMS320C64x DSP specifications