Reset Operation

Once the port is configured and the VCEN bit is set, the setting of other VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the capture counters begin counting. When BLKCAP is cleared, data capture and event generation may begin.

2.1.5Display Channel Reset

A software reset may be performed on the display channel by setting the RSTCH bit in VDCTL. This reset requires that the channel VCLKIN be trans- itioning. On display channel reset:

-No new DMA events are generated.

-Peripheral bus accesses are acknowledged (WREADY returned) to prevent DMA lock-up. (Write data may be written into the FIFO or discarded.)

-Channel display registers are set to their default values.

-Channel display FIFO is flushed (pointers reset).

-The VDEN bit in VDCTL is cleared to 0.

-The RSTCH bit self-clears to 0 after completion of the above.

Once the port is configured and the VDEN bit is set, the setting of other VDCTL bits (except VDEN, RSTCH, and BLKDIS) is prohibited and the display counters begin counting. Data outputs are driven (with default value, blanking, and control codes as appropriate and any control outputs are driven). When the BLKDIS bit is cleared, event generation may begin and FIFO data displayed.

2-4

Video Port

SPRU629

Page 36 Page 38
Page 37
Image 37
Texas Instruments TMS320C64x DSP manual Display Channel Reset
Page 36 Page 38

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
Top Page Image Contents