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Texas Instruments TMS320C64x DSP manual 4 BT.656 Data Sampling

Models: TMS320C64x DSP

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BT.656 Video Capture Mode

For the BT.656 video capture mode, the FIFO buffer is divided into three sec- tions (three buffers). One section is 1280 bytes deep and is dedicated for stor- age of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively. The buffers for Cb and Cr samples are each 640 bytes deep. The incoming video data stream is separated into Y, Cb, and Cr data streams, scaled (if selected), and the Y, Cb, and Cr buffers are filled. Each of the three buffers has a memory-mapped location associated with it; YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are read only and are used by DMAs to access video data samples stored in the FIFOs.

If video capture is enabled (BLKCAP bit in VCxCTL is cleared), pixels in the capture window are captured in the Y, Cb, and Cr buffers. The video capture module uses the YEVT, CbEVT, and CrEVT events to notify the DMA controller to copy data from the capture buffers to the DSP memory. The number of doublewords required to generate the events is set by the VCTHRLDn bits in VCxTHRLD. On every YEVT, the DMA should move data from the Y buffer to DSP memory using the YSRC location as the source address. On every CbEVT, the DMA should move data from the Cb buffer to DSP memory using the CBSRC location as the source address. On every CrEVT, the DMA should move data from the Cr buffer to DSP memory using the CRSRC location as the source address. Note that transfer size from the Cb and Cr buffers is half of the transfer size from the Y buffer since for every four Y samples, there are two Cb and two Cr samples.

3.2.4BT.656 Data Sampling

Incoming data (including timing codes) are sampled and the HCOUNT counter advanced only on clock cycles for which the CAPEN input is active. Inputs when CAPEN is inactive are ignored. The timing reference codes are recognized only when three sequential samples with CAPEN valid are the FFh, 00h, 00h sequence. A non-00h sample after the FFh or after the first 00h causes the timing reference recognition logic to be reset and to look for FFh again. (Unsampled data; those with CAPEN inactive; in the middle of a timing reference do not cause the recognition logic to be reset since these are not considered to be valid inputs.)

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Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual 4 BT.656 Data Sampling
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.