Video Capture FIFO Registers

3.14 Video Capture FIFO Registers

The capture FIFO mapping registers are listed in Table 3–34. These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers. The function of the video capture FIFO mapping registers is listed in Table 3–35.

Table 3–34. Video Capture FIFO Registers

Acronym

Register Name

YSRCA

Y FIFO Source Register A

CBSRCA

Cb FIFO Source Register A

CRSRCA

Cr FIFO Source Register A

YSRCB

Y FIFO Source Register B

CBSRCB

Cb FIFO Source Register B

CRSRCB

Cr FIFO Source Register B

 

 

Table 3–35. Video Capture FIFO Registers Function

 

Capture Mode

 

Register

BT.656 or Y/C

Raw Data

TSI

YSRCx

Maps Y capture buffer into DSP memory.

Maps data capture buffer

Maps data capture buffer

 

 

into the DSP memory.

into the DSP memory.

CBSRCx

Maps Cb capture buffer into DSP memory.

Not used.

Not used.

CRSRCx

Maps Cr capture buffer into DSP memory.

Not used.

Not used.

 

 

 

 

In BT.656 or Y/C capture mode, three DMAs move data from the Y, Cb, and Cr capture FIFOs to the DSP memory by using the memory-mapped YSRCx, CBSRCx, and CRSRCx registers. The DMA transfers are triggered by the YEVT, CbEVT, and CrEVT events, respectively.

In raw capture mode, one DMA channel moves data from the Y capture FIFO to the DSP memory by using the memory-mapped YSRCx register. The DMA transfers are triggered by a YEVT event.

The video port packs receive data into 64-bit words in the FIFO and the DMA should always move 64-bit-wide data from YSRCx, CBSRCx, and CRSRCx to the memory.

SPRU629

Video Capture Port

3-83

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Texas Instruments TMS320C64x DSP manual Video Capture Fifo Registers Function, Acronym Register Name

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

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For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

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In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.