Literature Number SPRU629 April
 Important Notice
 Read This First
 Trademarks
 Contents
 Video Capture Port
Discusses operation of the video capture port
 VCASTOP1, VCBSTOP1
VCASTRT1, VCBSTRT1
VCASTRT2, VCBSTRT2
VCASTOP2, VCBSTOP2
 11.1
 General Purpose I/O Operation
VDVSYNE2
 Vcxo Interpolated Control Port
 Figures
 Xii
 Figures Xiii
 Video Port
 Tables
 Xvi
 Tables Xvii
 Topic
Overview
 Video Port
 SPRU629
 VCTL3
VCLK1 VCLK2 VCTL1 VCTL2
Channel a
Channel B
 DMA Interface
Video Port Fifo
 Ysrca Cbsrca Crsrca Ysrcb Cbsrcb Crsrcb
Video Capture Fifo Configurations
 Ysrca
 Ysrca Cbsrca Crsrca
Y/C Video Capture Fifo Configuration
 Ydsta Cbdst Crdst
Video Display Fifo Configurations
 10-Bit Raw Video Display Fifo Configuration
 Ydstb
Ydsta
 Video Port Registers
10. Y/C Video Display Fifo Configuration
 Video Port Pin Mapping
Video Capture Signal Mapping
 Usage Raw Data Display Mode
Video Display Signal Mapping
 Data Bus 10-Bit 16-Bit 20-Bit Mode
Capture Mode BT.656 Raw Data
Vdin Bus Usage for Capture Modes
Vdin Data Bus Usage for Capture Modes
 Vdout Data Bus Usage for Display Modes
Vdout Data Bus Usage for Display Modes
 Video Port
 Reset Operation
Power-On Reset
Peripheral Bus Reset
 Capture Channel Reset
Software Port Reset
 Display Channel Reset
 Interrupt Operation
 Capture DMA Event Generation
DMA Operation
 Fifo ≥
Capture DMA Event Generation Flow Diagram
 Display DMA Event Generation
 Display DMA Event Generation Flow Diagram
 DMA Size and Threshold Restrictions
 DMA Interface Operation
 Video Port Functionality Subsets
Clocks
Video Port Functional Clocks
Data Bus Width
 Video Port Throughput and Latency
Fifo Size
Video Capture Throughput
 Bit Bit Dense 10-Bit
Y/C Video Capture Fifo Capacity
 Video Display Throughput
Raw Video Display Fifo Capacity
Bit Bit Dense 10/16-Bit 20-Bit Samples 5120 3840 2560 1280
 Video Port Control Registers
Video Port Control Registers
Acronym Register Name Section
 Video Port Control Register Vpctl Field Descriptions
Video Port Control Register Vpctl
Bit
Value Description
 VCLK2P
None Clear
None Reverse
None Activelow
 Video Port Operating Mode Selection
Operating Mode
Vpctl Bit
 Video Port Status Register Vpstat Field Descriptions
Video Port Status Register Vpstat
 Video Port Interrupt Enable Register Vpie
 Serrb
Ccmpb
Dcna
 Lfda
 Dcna Dcmp
Video Port Interrupt Status Register Vpis
Tick STC
Lfda Sfda VINTA2 VINTA1 Serra Ccmpa Covra
 Vcount = Ystop
 Vcbctl
 Out of the port. The DMA complete interrupt can be used to
 BT.656 or Y/C capture mode Lfda is set when long field
 Vcactl
 Video Capture Port
 Video Capture Mode Selection
Video Capture Mode Selection
TSI Bit Cmode Bits Mode Description
 1 BT.656 Capture Channels
BT.656 Video Capture Mode
 BT.656 Video Timing Reference Codes
2 BT.656 Timing Reference Codes
 BT.656 Protection Bits
Error Correction by Protection Bits
Line Information Bits Protection Bits
Received F, V, and H Bits
 3 BT.656 Image Window and Capture
010 011 100 101
P 0 Bits
 Common Video Source Parameters
Video Capture Parameters
 4 BT.656 Data Sampling
 Bit BT.656 Fifo Packing
5 BT.656 Fifo Packing
 VDIN9-0 / VDIN19-10 Cb Cr 0 Y Cb 1 Y
 Bit BT.656 Dense Fifo Packing
 Y/C Video Capture Mode
1 Y/C Capture Channels
2 Y/C Timing Reference Codes
 3 Y/C Image Window and Capture
 Bit Y/C Fifo Packing
4 Y/C Fifo Packing
 VDIN9-0 VDIN19-10 Little-Endian Packing Big-Endian Packing
 Bit Y/C Dense Fifo Packing
 Capture Determination and Notification
BT.656 and Y/C Mode Field and Frame Operation
 BT.656 and Y/C Mode Capture Operation
VC xCTL Bit
Operation
 VCxCTL Bit
Vertical Synchronization
 Vertical Counter Reset Point
Vertical Synchronization Programming
VC xCTL Bit VMode
 Vcount Operation Example EXC =
 Horizontal Synchronization
Horizontal Counter Reset Point
Horizontal Synchronization Programming
VCxCTL Bit HMode
 Hcount Operation Example EXC =
 Field Identification Programming
Field Identification
Field Detect Method
EAV code
 Short and Long Field Detect
11.Field 1 Detection Timing
 Video Input Filtering
10. Input Filter Mode Selection
Input Filter Modes
Filter Operation
 Scaling Operation
Chrominance Resampling Operation
 13 /2 Scaled Co-Sited Filtering
 Edge Pixel Replication
SAV
EAV
 Xstart Xsize SAV
16. Capture Window Not Requiring Edge Pixel Replication
 Ancillary Data Capture
Horizontal Ancillary Hanc Data Capture
Vertical Ancillary Vanc Data Capture
 Raw Data Capture Notification
Raw Data Capture Mode
 Raw Data Fifo Packing
11. Raw Data Mode Capture Operation
 17 -Bit Raw Data Fifo Packing
 19 -Bit Dense Raw Data Fifo Packing
 21 -Bit Raw Data Fifo Packing
 TSI Capture Mode
TSI Capture Features
TSI Data Capture
 TSI Capture Error Detection
Synchronizing the System Clock
Vclkin Capen Pacstrt
 Ctmode
PCR
 12. TSI Capture Mode Operation
TSI Data Capture Notification
Vcactl Bit
 Vclkin
Writing to the Fifo
TSI TSI Fifo
Perr
 Reading from the Fifo
Capture Line Boundary Conditions
 Fifo
Ipcount = IMGHSIZE78 Vclkout
 Capturing Video in BT.656 or Y/C Mode
 Handling Fifo Overrun in BT.656 or Y/C Mode
 Capturing Video in Raw Data Mode
 Handling Fifo Overrun Condition in Raw Data Mode
Capturing Data in TSI Capture Mode
 Handling Fifo Overrun Condition in TSI Capture Mode
 13. Video Capture Control Registers
Video Capture Registers
 Video Capture Channel x Status Register VCASTAT, Vcbstat
 Description Bit
BT.656 or Y/C Mode Raw Data Mode TSI Mode
 Value BT.656 or Y/C Mode Raw Data Mode TSI Mode
Vcfld
Detected
 Video Capture Channel a Control Register Vcactl
 Rdfe
Block
FIELD1
FIELD2
 FDL
Eavfid
V1EAV
V0EAV
 CON ‡
Half
 Description Raw Data Mode TSI Mode
 Vcystart
SSE
VCXSTART/VCVBLNKP
 Vcvblnkp
Vcxstart
 Vcxstop
Vcystop
 Field† Symval†
 FFFh Last captured line Not used
 VINT2
VIF2 FSCL2
VIF1
VINT1
 VIF2
 SPRU629
 VCTHRLD1
VCTHRLD2
 CAPEVTCT1
CAPEVTCT2
 Video Capture Channel B Control Register Vcbctl
Vrst Hrst Vcen PK10B Lfde Sfde Resmpl
CON Frame CF2 CF1
 F1C, F2C, and Frmc status bits, in VCBSTAT, are not
 EAV or Not used VCTL1 active edge
 Capture field Not used
CON‡
 Enstc Tcken Sten Ctmode
TSI Capture Control Register Tsictl
 24. TSI Capture Control Register Tsictl Field Descriptions
Value BT.656, Y/C Mode TSI Mode Or Raw Data Mode
 TSI Clock Initialization LSB Register Tsiclkinitl
BT.656, Y/C Mode TSI Mode Or Raw Data Mode
Inpcr
Bit Field
 TSI Clock Initialization MSB Register Tsiclkinitm
Inpcrm
Inpcre
 42. TSI System Time Clock LSB Register Tsistclkl
TSI System Time Clock LSB Register Tsistclkl
 TSI System Time Clock MSB Register Tsistclkm
Pcre Pcrm
Pcre
 ATC
TSI System Time Clock Compare LSB Register Tsistcmpl
 45. TSI System Time Clock Compare MSB Register Tsistcmpm
TSI System Time Clock Compare MSB Register Tsistcmpm
 Atcm
TSI System Time Clock Compare Mask LSB Register Tsistmskl
 TSI System Time Clock Compare Mask MSB Register Tsistmskm
 Tickct
TSI System Time Clock Ticks Interrupt Register Tsiticks
 Video Capture Fifo Registers
Capture Mode Register BT.656 or Y/C Raw Data
34. Video Capture Fifo Registers
35. Video Capture Fifo Registers Function
 Video Display Port
 Video Display Mode Selection
Video Display Mode Selection
Dmode Bits Mode Description
Image Timing
 Ntsc Compatible Interlaced Display
 Interlaced Blanking Intervals and Video Areas
 Video Display Counters
Progressive Blanking Intervals and Video Area
 Fpcount
Horizontal Blanking and Horizontal Sync Timing
 Flcount
Sync Signal Generation
Vblnk
Vsync
 Port Sync Operation
External Sync Operation
 Display Timing Reference Codes
BT.656 Video Display Mode
 Line Number
BT.656 Frame Timing
 11.Digital Vertical F and V Transitions
 3 BT.656 Image Display
Blanking Codes
 12 -Bit BT.656 Fifo Unpacking
4 BT.656 Fifo Unpacking
 13 -Bit BT.656 Fifo Unpacking
 14. BT.656 Dense Fifo Unpacking
 1 Y/C Display Timing Reference Codes
Y/C Video Display Mode
 2 Y/C Blanking Codes
3 Y/C Image Display
4 Y/C Fifo Unpacking
 16 -Bit Y/C Fifo Unpacking
 17 -Bit Y/C Fifo Unpacking
 18 -Bit Y/C Dense Fifo Unpacking
 Video Output Filtering
Output Filter Mode Selection
Output Filter Modes
Vdctl Bit
 19. Chrominance Resampling
 20 x Co-Sited Scaling
 23. Luma Edge Replication
 Ancillary Data Display
Raw Data Display Mode
Horizontal Ancillary Hanc Data Display
Vertical Ancillary Vanc Data Display
 Raw Data Fifo Unpacking
Raw Mode RGB Output Support
 26 -Bit Raw Fifo Unpacking
 28 -Bit Raw Fifo Unpacking
 30 -Bit Raw 3/4 Fifo Unpacking
 Display Determination and Notification
Video Display Field and Frame Operation
 CON Frame DF2 DF1
Display Operation
 Video Display Event Generation
 Display Line Boundary Conditions
 32. Display Line Boundary Example
 Interlaced BT.656 Timing Example
Display Timing Examples
 33. BT.656 Interlaced Display Horizontal Timing Example
 SPRU629
 34. BT.656 Interlaced Display Vertical Timing Example
 Interlaced Raw Display Example
 35. Raw Interlaced Display Horizontal Timing
 SPRU629
 36. Raw Interlaced Display Vertical Timing Example
 3 Y/C Progressive Display Example
 37. Y/C Progressive Display Horizontal Timing Example
 SPRU629
 38. Y/C Progressive Display Vertical Timing Example
 Displaying Video in BT.656 or Y/C Mode
 Displaying Video in BT.656 or Y/C Mode
 Displaying Video in Raw Data Mode
 Displaying Video in Raw Data Mode
 Handling Underrun Condition of the Display Fifo
 Video Display Control Registers
Video Display Registers
 Video Display Status Register Vdstat
 Video Display Status Register Vdstat Field Descriptions
 BT.656 and Y/C Mode Raw Data Mode
Video Display Control Register Vdctl
Video Display Control Register Vdctl Field Descriptions
 Blkdis
Disable Enable
FXS
Output
 Value BT.656 and Y/C Mode Raw Data Mode
 Blanking
Rgbx
 Flddis
Frmdis
 Video Display Frame Size Register Vdfrmsz
Frmheight
Frmwidth
 Hbdla
Video Display Horizontal Blanking Register Vdhblnk
 Delay
Hblnkstop
Hblnkstart
 VBLNKXSTART1
VBLNKYSTART1
 VBLNKXSTOP1
VBLNKYSTOP1
 Field† Symval†
 VBLNKXSTART2
VBLNKYSTART2
 VBLNKXSTOP2
VBLNKYSTOP2
 Video Display Field 1 Image Offset Register VDIMGOFF1
 IMGVOFF1
IMGHOFF1
Negoff
 Video Display Field 1 Image Size Register VDIMGSZ1
IMGVSIZE1
IMGHSIZE1
 Video Display Field 2 Image Offset Register VDIMGOFF2
IMGVOFF2
IMGHOFF2
 None
 Video Display Field 2 Image Size Register VDIMGSZ2
IMGVSIZE2
IMGHSIZE2
 Video Display Field 1 Timing Register VDFLDT1
FLD1YSTART
FLD1XSTART
 Video Display Field 2 Timing Register VDFLDT2
FLD2YSTART
FLD2XSTART
 Incpix
Video Display Threshold Register Vdthrld
 VDTHRLD1
VDTHRLD2
 Video Display Horizontal Synchronization Register Vdhsync
Hsyncstop
Hsyncstart
 VSYNCXSTART1
VSYNCYSTART1
 VSYNCXSTOP1
VSYNCYSTOP1
 VSYNCXSTART2
VSYNCYSTART2
 VSYNCXSTOP2
VSYNCYSTOP2
 Vrld
Video Display Counter Reload Register Vdreload
Hrld
Crld
 Video Display Display Event Register Vddispevt
DISPEVT2
DISPEVT1
 Clipchigh
Video Display Clipping Register Vdclip
Clipyhigh Clipylow
Clipclow
 Video Display Default Display Value Register Vddefval
Crdefval Cbdefval
Ydefval
 Crdefval
Defval
 64. Video Display Vertical Interrupt Register Vdvint
Video Display Vertical Interrupt Register Vdvint
 Video Display Field Bit Register Vdfbit
Fbitset
Fbitclr
 VBITSET1
VBITCLR1
 Field† Symval†
 VBITSET2
VBITCLR2
 Field† Symval†
 Video Display Registers Recommended Values
34. Video Display Register Recommended Values
Register Field 525/60 Value 625/50 Value
 VDVSYNE2 VSYNCXSTOP2
VDVSYNS2 VSYNCXSTART2
Vdfbit Fbitclr Fbitset
VDVBIT1 VBITSET1
 35. Video Display Fifo Registers
Video Display Fifo Registers
36. Video Display Fifo Registers Function
Register BT.656 or Y/C Raw Data
 Gpio Registers
General Purpose I/O Operation
 Video Port Registers
Gpio Registers
 Type
Video Port Peripheral Identification Register Vppid
Class Revision
Class
 Soft Free
Video Port Peripheral Control Register PCR
 Soft
Peren
Stop
Comp
 Video Port Pin Function Register Pfunc Field Descriptions
Video Port Pin Function Register Pfunc
PFUNC22
Normal
 PFUNC10
PFUNC20
VDATA10TO19
PFUNC0
 Video Port Pin Direction Register Pdir Field Descriptions
Video Port Pin Direction Register Pdir
PDIR22
VCTL3IN
 VCTL2IN
PDIR21
VCTL2OUT
PDIR20
 VDATA8TO9IN
PDIR8
VDATA8TO9OUT
PDIR4
 PDIN20
Video Port Pin Data Input Register Pdin
PDIN12
PDIN7 PDIN6
 Video Port Pin Data Input Register Pdin Field Descriptions
 Video Port Pin Data Output Register Pdout
 Video Port Pin Data Out Register Pdout Field Descriptions
PDOUT21
PDOUT20
 Video Port Pin Data Set Register Pdset
 Video Port Pin Data Set Register Pdset Field Descriptions
PDSET21
PDSET20
 Video Port Pin Data Clear Register Pdclr
Video Port Pin Data Clear Register Pdclr
 Video Port Pin Data Clear Register Pdclr Field Descriptions
 Video Port Pin Interrupt Enable Register Pien
Video Port Pin Interrupt Enable Register Pien
 PIEN20
PIEN21
 PIPOL21 PIPOL20 PIPOL19
Video Port Pin Interrupt Polarity Register Pipol
PIPOL17 PIPOL16 PIPOL15
PIPOL13 PIPOL12
 VCTL3ACTHI
PIPOL22
VCTL3ACTLO
PIPOL21
 Video Port Pin Interrupt Status Register Pistat
 VCTL3INT
PISTAT22
VCTL2INT
PISTAT20
 PICLR4
Video Port Pin Interrupt Clear Register Piclr
 PICLR22
PICLR21
PICLR20
 Vcxo Interpolated Control Port
 Overview
 VIC Port Signal Direction Description
VIC Port Interface Signals
Interface
Operational Details
 Example Values for Interpolation Rate
 Enabling VIC Port
VIC Port Registers
VIC Port Registers
 VIC Control Register Vicctl Field Descriptions
VIC Control Register Vicctl
 GO bit can be written to at any time
 VIC Input Register Vicin
VIC Input Register Vicin Field Descriptions
Vicinbits
 VIC Clock Divider Register Vicdiv
VIC Clock Divider Register Vicdiv Field Descriptions
Vicclkdiv
 Video Port Configuration Examples
 VCAIMGHSIZE2 * VCAIMGVSIZE2
Example 1 Noncontinuous Frame Capture for 525/60 Format
 Frame
 VPVCASTOP1RMKVCAYSTOP1, VCAXSTOP1
 VPVCASTRT1SSEENABLE, VCAXSTART1
 Vpvcactlblkcapclear
 SPRU629
 Vcayedmafrmcnt
 Edmaoptrmk Edmaoptprimedium
 Vdhblnkstop Vdhblnkstart +
Example 2 Noncontinuous Frame Display for 525/60 Format
 Define vertical blanking bitVDVBITn reg values
 VDIMGHSIZE1 * VDIMGVSIZE1
 Dmode
 VPVDFRMSZRMKVDFRMHEIGHT, Vdfrmwidth
 VPVDVBLKS2RMKVDVBLNKYSTART2, VDVBLNKXSTART2
 VPVDVSYNE2RMKVDVSYNCYSTOP2, VDVSYNCXSTOP2
 Vpvdstatfrmdclear
 Vdyedmafrmcnt Vdyedmaelecnt
 Example 2 Noncontinuous Frame Display for 525/60 Format
 EDMAOPT2DSYES
 Index
 Index-2
 Index-3
 Pin data set register Pdset Pin direction register Pdir
 Vcaevtct
 Vdhblnk
 Index-7
 Vddefval Vddispevt
 Index-9
 Ydsta Ydstb