TSI Capture Mode

The system time clock counter is initialized by software with the PCR of the first packet with a PCR header. After initialization, the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values.

The system time is made available to the DSP at any time through the system time clock registers (TSISTCLKL and TSISTCLKM). The DSP can program the video port to interrupt the DSP whenever a specific system time is reached or whenever a specific number of system time clock cycles have elapsed.

3.8.5TSI Data Capture Notification

Since TSI mode captures only data packets, there is no need for field control. Some flexibility in capture and DSP notification is still provided in order to accommodate various DMA structures and processing flows. Each TSI data packet is treated similar to a progressive scan video frame. The TSI mode uses the CON and FRAME bits of VCACTL in a slightly different manner, as listed in Table 3–12.

The CON bit controls the capture of multiple packets. When CON = 1, continuous capture is enabled, the video port captures incoming data packets (assuming the VCEN bit is set) without the need for DSP interaction. It relies on a DMA structure with circular buffering capability to service the capture FIFO. When CON = 0, continuous capture is disabled, the video port sets the frame capture complete bit (FRMC) in VCASTAT upon the capture of each packet. Once the capture complete bit is set, at most, one more frame can be received before capture operation is halted (as determined by the FRAME bit state). This prevents subsequent data from overwriting previous packets until the DSP has a chance to update DMA pointers or process those packets.

Table 3–12. TSI Capture Mode Operation

VCACTL Bit

CON

FRAME

CF2

CF1

Operation

0

0

x

x

Noncontinuous packet capture. FRMC is set after packet capture and

 

 

 

 

causes CCMPA to be set. Capture will halt upon completion of the next

 

 

 

 

data packet unless the FRMC bit is cleared. (DSP has the entire next

 

 

 

 

data packet time to clear FRMC.)

0

1

x

x

Single packet capture. FRMC is set after packet capture and causes

 

 

 

 

CCMPA to be set. Capture is halted until the FRMC bit is cleared.

1

0

x

x

Continuous packet capture. FRMC is set after packet capture and

 

 

 

 

causes CCMPA to be set (CCMPx interrupt can be disabled). The port

 

 

 

 

will continue capturing packets regardless of the state of FRMC.

1

1

x

x

Reserved

 

 

 

 

 

3-40

Video Capture Port

SPRU629

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Texas Instruments TMS320C64x DSP manual TSI Data Capture Notification, TSI Capture Mode Operation, Vcactl Bit
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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