Texas Instruments TMS320C64x DSP manual TSI Data Capture Notification, TSI Capture Mode Operation

TSI Capture Mode

The system time clock counter is initialized by software with the PCR of the first packet with a PCR header. After initialization, the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values.

The system time is made available to the DSP at any time through the system time clock registers (TSISTCLKL and TSISTCLKM). The DSP can program the video port to interrupt the DSP whenever a specific system time is reached or whenever a specific number of system time clock cycles have elapsed.

3.8.5TSI Data Capture Notification

Since TSI mode captures only data packets, there is no need for field control. Some flexibility in capture and DSP notification is still provided in order to accommodate various DMA structures and processing flows. Each TSI data packet is treated similar to a progressive scan video frame. The TSI mode uses the CON and FRAME bits of VCACTL in a slightly different manner, as listed in Table 3–12.

The CON bit controls the capture of multiple packets. When CON = 1, continuous capture is enabled, the video port captures incoming data packets (assuming the VCEN bit is set) without the need for DSP interaction. It relies on a DMA structure with circular buffering capability to service the capture FIFO. When CON = 0, continuous capture is disabled, the video port sets the frame capture complete bit (FRMC) in VCASTAT upon the capture of each packet. Once the capture complete bit is set, at most, one more frame can be received before capture operation is halted (as determined by the FRAME bit state). This prevents subsequent data from overwriting previous packets until the DSP has a chance to update DMA pointers or process those packets.

Table 3–12. TSI Capture Mode Operation

VCACTL Bit

CON	FRAME	CF2	CF1	Operation
0	0	x	x	Noncontinuous packet capture. FRMC is set after packet capture and
				causes CCMPA to be set. Capture will halt upon completion of the next
				data packet unless the FRMC bit is cleared. (DSP has the entire next
				data packet time to clear FRMC.)
0	1	x	x	Single packet capture. FRMC is set after packet capture and causes
				CCMPA to be set. Capture is halted until the FRMC bit is cleared.
1	0	x	x	Continuous packet capture. FRMC is set after packet capture and
				causes CCMPA to be set (CCMPx interrupt can be disabled). The port
				will continue capturing packets regardless of the state of FRMC.
1	1	x	x	Reserved

3-40 Video Capture Port SPRU629