Texas Instruments TMS320C64x DSP manual

4-40Video Display Port

SPRU629

Figure 4–35. Raw Interlaced Display Horizontal Timing

VCLKIN

					414	One Line						2112				Next Line
						One Line										Next Line
FPCOUNT	720	721	735	736	799	800	857	0	1	7	8	9	711	712	719	720	721
IPCOUNT	703	703	703	703	703	703	703	703	703	703	0	1	703	703	703	703	703

VCTL1 (HBLNK)† §

VCTL1 (HSYNC)† §

VCLKOUT

Display Image

Blanking

Active Video

VDOUT[19–0] §

FLCOUNT

n – 1

Raw2108 (B702) Raw2109 (R703)

Raw2110 (G703) Raw2111 (B703)

n + 1

Default Value Default Value Default Value Default Value Default Value

Default Value Default Value Default Value Default Value Default Value Default Value

Default Value Default Value Default Value

Raw0 (R0)

Raw1 (G0)

Raw2 (B0)

Raw3 (R1) Raw4 (G1) Raw5 (B1)

Default Value

Default Value Default Value Default Value Default Value Default Value

FRMWIDTH = 858

IMGHOFF1 = 8

HSYNCSTART = 736

HBLNKSTART = 720

IMGHSIZE1 = 704

HSYNCSTOP = 800

HBLNKSTOP = 0

IMGHOFF2 = 8

IMGHSIZE2 = 704

INCPIX = 3

†Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.

§Diagram assumes a two VCLK pipeline delay between internal counters and output signals.

Display Timing Examples

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual Raw Interlaced Display Horizontal Timing

Models: TMS320C64x DSP