4 Y/C Fifo Packing | Texas Instruments TMS320C64x DSP instruction

Y/C Video Capture Mode

3.3.4Y/C FIFO Packing

Captured data is always packed into 64 bits before being written into the capture FIFO(s). The packing and byte ordering is dependant upon the capture data size and the device endian mode. For little-endian operation (default), data is packed into the FIFO from right to left; for big-endian opera- tion, data is packed from left to right.

The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are packed into each word as shown in Figure 3–5.

Figure 3–5. 8-Bit Y/C FIFO Packing

VCLKINA

VDIN[9–2]

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

Y 8

Y 9

Y 10

Y 11

VDIN[19–12]

Cb 0

Cr 0

Cb 1

Cr 1

Cb 2

Cr 2

Cb 3

Cr 3

Cb 4

Cb 5

Cr 5

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Y FIFO

Y 31	Y 30	Y 29	Y 28	Y 27	Y 26	Y 25	Y 24
Y 23	Y 22	Y 21	Y 20	Y 19	Y 18	Y 17	Y 16
Y 15	Y 14	Y 13	Y 12	Y 11	Y 10	Y 9	Y 8
Y 7	Y 6	Y 5	Y 4	Y 3	Y 2	Y 1	Y 0

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Cb FIFO

Cb 15	Cb 14	Cb 13	Cb 12	Cb 11	Cb 10	Cb 9	Cb 8
Cb 7	Cb 6	Cb 5	Cb 4	Cb 3	Cb 2	Cb 1	Cb 0

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Cr FIFO

YFIFO

Cb FIFO

Cr 15

Cr 14

Cr 13

Cr 12

Cr 11

Cr 10

Cr 9

Cr 8

Cr 7

Cr 6

Cr 5

Cr 4

Cr 3

Cr 2

Cr 1

Cr 0

Little-Endian Packing

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Y 24

Y 25

Y 26

Y 27

Y 28

Y 29

Y 30

Y 31

Y 16

Y 17

Y 18

Y 19

Y 20

Y 21

Y 22

Y 23

Y 8

Y 9

Y 10

Y 11

Y 12

Y 13

Y 14

Y 15

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Cb 8

Cb 9

Cb 10

Cb 11

Cb 12

Cb 13

Cb 14

Cb 15

Cb 0

Cb 1

Cb 2

Cb 3

Cb 4

Cb 5

Cb 6

Cb 7

56 55

48 47

40 39

32 31

24 23

16 15

8 7

Cr FIFO

Cr 8	Cr 9	Cr 10	Cr 11	Cr 12	Cr 13	Cr 14	Cr 15
Cr 0	Cr 1	Cr 2	Cr 3	Cr 4	Cr 5	Cr 6	Cr 7

Big-Endian Packing

3-14

Video Capture Port

SPRU629

TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.

Texas Instruments TMS320C64x DSP manual 4 Y/C Fifo Packing, Bit Y/C Fifo Packing

Models: TMS320C64x DSP

3.3.4Y/C FIFO Packing

Figure 3–5. 8-Bit Y/C FIFO Packing

TMS320C64x DSP specifications