TSI Capture Mode

3.8.6Writing to the FIFO

The captured TSI packet data and the associated timestamps are written into the receive FIFO. The packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and timestamp writes into the FIFO. The FIFO data packing is shown in Figure 3–25.

Figure 3–25. TSI FIFO Packing

VCLKIN

 

 

 

VDIN[9–2]TSI 0 TSI 1 TSI 2 TSI 3 TSI 4 TSI 5

TSI 6 TSI 7 TSI 8 TSI 9 TSI 10 TSI 11

 

 

63

56 55

48 47

40 39

32 31

24 23

16 15

8 7

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSI 15

 

TSI 14

 

TSI 13

 

TSI 12

 

TSI 11

 

TSI 10

 

TSI 9

 

TSI 8

TSI FIFO

 

TSI 7

 

TSI 6

 

TSI 5

 

TSI 4

 

TSI 3

 

TSI 2

 

TSI 1

 

TSI 0

 

 

 

 

 

 

 

Little-Endian Packing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

56 55

48 47

40 39

32 31

24 23

16 15

8 7

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSI 8

 

TSI 9

 

TSI 10

 

TSI 11

 

TSI 12

 

TSI 13

 

TSI 14

 

TSI 15

TSI FIFO

 

TSI 0

 

TSI 1

 

TSI 2

 

TSI 3

 

TSI 4

 

TSI 5

 

TSI 6

 

TSI 7

 

 

 

 

 

 

 

Big-Endian Packing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The data capture circuitry signals to the synchronizing circuit when to take a timestamp of the hardware counters. The FIFO write controller keeps track of number of bytes received in a packet. It multiplexes the timestamp data and the packet data onto the FIFO write data bus. The timestamp and packet error information are inserted after each packet in the FIFO and must use the correct endian byte ordering. The format for the timestamp is shown in Figure 3–26 and Figure 3–27.

Figure 3–26. TSI Timestamp Format (Little Endian)

63

62

61

42

41

33

32

PERR

PSTERR

Reserved

 

PCR extension

PCR

 

 

 

 

 

 

 

31

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

PCR

 

 

 

 

 

 

 

 

 

 

 

SPRU629

Video Capture Port

3-41

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Texas Instruments TMS320C64x DSP manual Writing to the Fifo, Vclkin, TSI TSI Fifo, Perr
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TMS320C64x DSP specifications

The TMS320C64x DSP family from Texas Instruments represents a significant milestone in the realm of digital signal processing. Launched as part of the C6000 series, the C64x DSPs are designed for high-performance applications requiring intensive computational capabilities, such as telecommunications, audio processing, video processing, and industrial control systems.

One of the standout features of the TMS320C64x DSP is its VLIW (Very Long Instruction Word) architecture, which allows for an exceptionally high level of parallelism. This architecture enables multiple instructions to be executed simultaneously, boosting the overall throughput and allowing for complex data processing tasks to be completed more quickly than with conventional DSPs.

The C64x DSPs also boast an impressive clock frequency range, typically up to 1 GHz, delivering substantial computational power for real-time processing goals. Additionally, these processors feature extensive on-chip memory, including L1 and L2 cache, which significantly enhances data access speeds and helps reduce bottlenecks during high-demand processing tasks.

Another key characteristic of the TMS320C64x family is its support for advanced instruction sets optimized for specific applications. These include SIMD (Single Instruction, Multiple Data) capabilities, allowing for efficient handling of large datasets often involved in multimedia processing or complex signal manipulation.

For connectivity, these DSPs often integrate advanced interfaces such as EMIF (External Memory Interface) and McBSP (Multichannel Buffered Serial Port), facilitating seamless interaction with a variety of peripheral devices. This ensures that the DSP can suit different application needs and integrate well into various system architectures.

Texas Instruments emphasizes low power consumption with the C64x DSPs, making them ideal for portable or energy-sensitive applications. Advanced power management techniques and technologies, such as dynamic voltage and frequency scaling, are incorporated to further enhance energy efficiency without compromising performance.

In summary, the Texas Instruments TMS320C64x DSP family stands out due to its high-performance capabilities driven by a VLIW architecture, high clock speeds, extensive memory options, a rich instruction set, and advanced connectivity features, all while maintaining power efficiency. These characteristics make it an exceptional choice for developers looking to integrate robust digital signal processing into their applications, whether in telecommunications, audio and video processing, or embedded control systems.
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